The disclosure relates to technology for shifting a frequency range of a signal. In one aspect, a circuit comprises a frequency mixer, a frequency synthesizer configured to generate an oscillator signal, a programmable driver, and a controller. The programmable driver is configured to receive the oscillator signal from the frequency synthesizer and to provide the oscillator signal to the oscillator input of the frequency mixer. The programmable driver is configured to have a variable drive strength. The controller is configured to control the drive strength of the programmable driver based on a frequency of the oscillator signal to adjust a rise time and a fall time of the oscillator signal at the oscillator input of the frequency mixer.

Disclosed herein is an innovative multi-layer hybrid/digital MIMO architecture that comprises single-stream or fully-connected (FC) multi-stream beamforming tiles (with RF complex-weights) in the first layer, followed by a fully connected (analog/digital) baseband layer. This architecture overcomes the complexity versus spectral-efficiency tradeoffs of existing hybrid MIMO architectures and enables MIMO stream/user scalability, superior energy-efficiency, and spatial-processing flexibility.

With advanced compute capabilities and growing convergence of wireless standards, it is desirable to run multiple wireless standards, e.g., 4G, 5G NR, and Wi-Fi, on a single signal processing system. Automatic gain control (AGC) is a process of converging on a gain level for optimum signal reception considering the dynamic range of all the components in the receive chain, including analog and digital parts. For certain wireless standard such as Wi-Fi, AGC is required to complete within a short interval. Both RF and baseband gains have to be adjusted within this short time. Discloses in the present disclosure are embodiments of a high-speed and low pin-count interface between an RF circuit and a baseband circuit for AGC communication. The high-speed interface provides a light-weight serial protocol over one or more low-voltage differential signaling (LVDS) channels to meet a low-latency requirement for gain updates.

A task processor has a low power connectivity processor and a high performance applications processor. Software processes have a component operative on a connectivity processor and a component operative on an applications processor. The low power connectivity processor is coupled to a low power front end for wireless packets and the high performance applications processor is coupled to a high performance front end. A power controller is coupled to the low power front end and enables the applications processor and high performance front end when wireless packets which require greater processing capacity are received, and removes power from the applications processor and high performance front end at other times.

A radio frequency transmitter includes an upconverter that outputs in-phase (I) and quadrature (Q) signals, a digital timing offset circuit, first and second digital-to-analog converters (DACs), an analog timing offset removal circuit, first and second pulse shapers, and an adder. The digital timing offset circuit introduces a time offset between the I and Q signals. The first and second DACs output analog I and Q signals, respectively, and have first and second clock signals, respectively. The first and second clock signals have the same frequency and are offset relative to each other by the time offset. The analog timing offset removal circuit removes the time offset between the analog I and Q signals. The first and second pulse shapers receive the analog I and Q signals, respectively, and output pulse-shaped I and Q signals. The adder receives the pulse-shaped I and Q signals and outputs an intermediate frequency signal.

With advanced compute capabilities and growing convergence of wireless standards, it is desirable to run multiple wireless standards, e.g., 4G, 5G NR, and Wi-Fi, on a single signal processing system. Automatic gain control (AGC) is a process of converging on a gain level for optimum signal reception considering the dynamic range of all the components in the receive chain, including analog and digital parts. For certain wireless standard such as Wi-Fi, AGC is required to complete within a short interval. Both RF and baseband gains have to be adjusted within this short time. Discloses in the present disclosure are embodiments of a high-speed and low pin-count interface between an RF circuit and a baseband circuit for AGC communication. The high-speed interface provides a light-weight serial protocol over one or more low-voltage differential signaling (LVDS) channels to meet a low-latency requirement for gain updates.

A receiver path circuit includes a first stage, a down-sampler and a second stage. The first stage is configured to filter a mixer-output-signal received from a mixer and provide a first-stage-output-signal. The down-sampler is configured to down-sample the first-stage-output-signal to provide a transition-signal having a transition-frequency. The transition-frequency is lower than the frequency of the first-stage-output-signal. The second stage includes a switched-capacitor circuit that is configured to filter and reduce the frequency of the transition-signal in order to provide a second-stage-output-signal to an ADC.

In one embodiment an apparatus includes: a mixer to downconvert a radio frequency (RF) spectrum including at least a first RF signal of a first channel of interest and a second RF signal of a second channel of interest to at least a first second frequency signal and a second second frequency signal; a first digitizer to digitize the first second frequency signal to a first digitized signal, the first digitizer configured to operate as a low-pass analog-to-digital converter (ADC); a second digitizer to digitize the second second frequency signal to a second digitized signal, the second digitizer configured to operate as a band-pass ADC; and a digital processor to digitally process the first digitized signal and the second digitized signal.

A radio frequency module and a communication device capable of further suppressing a decrease in reception sensitivity are provided. A radio frequency module includes a switch (second switch), a reception filter (second reception filter), a low-noise amplifier (second low-noise amplifier), and a filter (second filter). The switch is configured to change over between a transmission path of a transmission signal and a reception path of a reception signal in communication based on a time division duplex system. The reception filter is provided at a subsequent stage of the switch and is configured to pass the reception signal in a predetermined frequency band. The low-noise amplifier is configured to amplify the reception signal that has passed through the reception filter. The filter is provided at a preceding stage of the switch in the reception path (second reception path).

Embodiments of the invention include a wakeup receiver (WRX) featuring a charge-domain analog front end (AFE) with parallel radio frequency (RF) rectifier, charge-transfer summation amplifier (CTSA), and successive approximation analog-to-digital converter (SAR ADC) stages. The WRX operates at very low power and exhibits above-average sensitivity, random pulsed interferer rejections, and yield over process.