A multi-mode antenna tuner circuit and related apparatus are provided. The multi-mode antenna tuner circuit can be configured to operate in a low-current mode or a high-power mode. When operating in the high-power mode, the multi-mode antenna tuner circuit can provide full-fledged functionalities and consume a higher amount of current. In contrast, in the low-current mode, the multi-mode antenna tuner circuit provides reduced functionality and consumes a lower amount of current. In this regard, in a wireless communication apparatus employing multiple multi-mode antenna tuner circuits, it is possible to opportunistically configure some multi-mode antenna tuner circuits to operate in the low-current mode based on an operating environment (e.g., frequency band, location, etc.) and internal state (e.g., battery level, signal strength, etc.) of the wireless communication apparatus. As a result, it may be possible to reduce consumption and heat dissipation without compromising performance of the wireless communication apparatus.

A receiving apparatus includes at least two first radio frequency signal processors and a first analog signal processor. The at least two first radio frequency signal processors are coupled to the first analog signal processor using at least one first switch circuit. The first radio frequency signal processor is configured to obtain a radio frequency signal to obtain a first analog signal. The first analog signal processor is configured to obtain a first baseband signal based on the first analog signal.

A receiving apparatus includes at least two first radio frequency signal processors and a first analog signal processor. The at least two first radio frequency signal processors are coupled to the first analog signal processor using at least one first switch circuit. The first radio frequency signal processor is configured to obtain a radio frequency signal to obtain a first analog signal. The first analog signal processor is configured to obtain a first baseband signal based on the first analog signal.

Provided is a two-dimensional phased array antenna having a simple configuration capable of reducing the number of control systems and the number of control input ports for phase control of antenna elements. The phased array antenna comprises a plurality of antenna elements arranged in a first direction and a second direction intersecting the first direction, a plurality of frequency mixers for respectively supplying transmission signals with a predetermined transmission frequency (f) to the plurality of antenna elements, and means for generating a plurality of first mixing signals having a predetermined first phase difference (Δφ.sub.1) between the antenna elements adjacent to each other in the first direction and a plurality of second mixing signals having a predetermined second phase difference (Δφ.sub.2) between the antenna elements adjacent to each other in the second direction, based on three frequency-controllable input signals with respective frequencies different from each other, and supplying the plurality of first mixing signals and the plurality of second mixing signals to the plurality of frequency mixers.

A radio frequency apparatus includes a power amplifier circuit, a signal coupling circuit, an extraction circuit, and a harmonic filter circuit. The power amplifier circuit is configured to amplify a differential signal to output a to-be-filtered signal. The signal coupling circuit includes a primary side inductor and a secondary side inductor. The signal coupling circuit is configured to convert the to-be-filtered signal received by the primary side inductor into a single-ended signal outputted from the secondary side inductor. The extraction circuit has a center tap. The extraction circuit is configured to inductively couple to the primary side inductor and output a common mode signal from the center tap. The harmonic filter circuit is configured to perform a harmonic filtering on the single-ended signal according to the common mode signal, such that the secondary side inductor of the signal coupling circuit outputs a filtered signal.

A radio frequency apparatus includes a power amplifier circuit, a signal coupling circuit, an extraction circuit, and a harmonic filter circuit. The power amplifier circuit is configured to amplify a differential signal to output a to-be-filtered signal. The signal coupling circuit includes a primary side inductor and a secondary side inductor. The signal coupling circuit is configured to convert the to-be-filtered signal received by the primary side inductor into a single-ended signal outputted from the secondary side inductor. The extraction circuit has a center tap. The extraction circuit is configured to inductively couple to the primary side inductor and output a common mode signal from the center tap. The harmonic filter circuit is configured to perform a harmonic filtering on the single-ended signal according to the common mode signal, such that the secondary side inductor of the signal coupling circuit outputs a filtered signal.

An electronic device may comprise antenna, low-noise amplifier, radio frequency integrated circuit (RFIC), and communication. The communication processor may be configured to identify a low-noise amplifier for amplifying a first RF signal and a low-noise amplifier for amplifying a second RF signal, based on the low-noise amplifier for amplifying the first RF signal differing from the low-noise amplifier for amplifying the second RF signal, set a first gain of the low-noise amplifier for amplifying the first RF signal, set a second gain of the low-noise amplifier for amplifying the second RF signal, based on the low-noise amplifier for amplifying the first RF signal being identical to the low-noise amplifier for amplifying the second RF signal, set a third gain of a low-noise amplifier of amplifying the first RF signal and the second RF signal.

A first physical layer device includes a first transmitter and a first receiver. The first transmitter transmits first data to a second physical layer device over a medium at a first line rate during a first transmit period. The first receiver is configured to not receive data during the first transmit period and an echo reflection period occurring after the first transmit period. The echo reflection period is based on a length of the medium between the first physical layer device and the second physical layer device. The first receiver is configured to, after the echo reflection period, receive second data from the second physical layer device over the medium at a second line rate that is less than the first line rate.

A first physical layer device includes a first transmitter and a first receiver. The first transmitter transmits first data to a second physical layer device over a medium at a first line rate during a first transmit period. The first receiver is configured to not receive data during the first transmit period and an echo reflection period occurring after the first transmit period. The echo reflection period is based on a length of the medium between the first physical layer device and the second physical layer device. The first receiver is configured to, after the echo reflection period, receive second data from the second physical layer device over the medium at a second line rate that is less than the first line rate.

In a transmitter there is a distributor and assembly bank into which a predetermined quantity of an input payload from a source is repeatedly written according to a first distributor permutation to create as many input vectors as there are electromagnetic propagation pathways. A staging bank exists into which each input vector available from the assembly bank are repeatedly written according to a second distributor permutation. A presentation bank exists into which each input vector available from the staging bank are repeatedly written according to a third distributor permutation. One or more encoders repeatedly encode input vectors from the presentation bank; there being as many encoders as electromagnetic propagation pathways, and each encoder makes available each encoded ordered series of output levels for communication over the pathways. The banks and encoders are in up to four timing domains. A corresponding receiver, decoder, and reception, staging and disassembly banks and a sink are at the end of the pathways.