A receiving apparatus includes at least two first radio frequency signal processors and a first analog signal processor. The at least two first radio frequency signal processors are coupled to the first analog signal processor using at least one first switch circuit. The first radio frequency signal processor is configured to obtain a radio frequency signal to obtain a first analog signal. The first analog signal processor is configured to obtain a first baseband signal based on the first analog signal.

A receiving apparatus includes at least two first radio frequency signal processors and a first analog signal processor. The at least two first radio frequency signal processors are coupled to the first analog signal processor using at least one first switch circuit. The first radio frequency signal processor is configured to obtain a radio frequency signal to obtain a first analog signal. The first analog signal processor is configured to obtain a first baseband signal based on the first analog signal.

Receiver circuitry for a communication system includes signal processing circuitry, voltage digital-to-analog converter (DAC) circuitry, and slicer circuitry. The signal processing circuitry receives a data signal and generate a processed data signal. The voltage DAC circuitry generates a first threshold reference voltage. The slicer circuitry is coupled to an output of the signal processing circuitry. The slicer circuitry includes a capture flip-flop (CapFF) circuit that receives the processed data signal and the first threshold reference voltage. The CapFF circuit further generates a first data signal. The first CapFF circuit includes a first offset compensation circuit that adjusts a parasitic capacitance of the first CapFF circuit.

Receiver circuitry for a communication system includes signal processing circuitry, voltage digital-to-analog converter (DAC) circuitry, and slicer circuitry. The signal processing circuitry receives a data signal and generate a processed data signal. The voltage DAC circuitry generates a first threshold reference voltage. The slicer circuitry is coupled to an output of the signal processing circuitry. The slicer circuitry includes a capture flip-flop (CapFF) circuit that receives the processed data signal and the first threshold reference voltage. The CapFF circuit further generates a first data signal. The first CapFF circuit includes a first offset compensation circuit that adjusts a parasitic capacitance of the first CapFF circuit.

A first physical layer device includes a first transmitter and a first receiver. The first transmitter transmits first data to a second physical layer device over a medium at a first line rate during a first transmit period. The first receiver is configured to not receive data during the first transmit period and an echo reflection period occurring after the first transmit period. The echo reflection period is based on a length of the medium between the first physical layer device and the second physical layer device. The first receiver is configured to, after the echo reflection period, receive second data from the second physical layer device over the medium at a second line rate that is less than the first line rate.

A first physical layer device includes a first transmitter and a first receiver. The first transmitter transmits first data to a second physical layer device over a medium at a first line rate during a first transmit period. The first receiver is configured to not receive data during the first transmit period and an echo reflection period occurring after the first transmit period. The echo reflection period is based on a length of the medium between the first physical layer device and the second physical layer device. The first receiver is configured to, after the echo reflection period, receive second data from the second physical layer device over the medium at a second line rate that is less than the first line rate.

A three-level encoding transmitter is disclosed in which a transmitter circuit is configured to receive an input data signal including binary data and transmit an encoded data signal. The transmitter circuit can include an inverter circuit configured transmit first and second voltages for each logical level of the binary data. A transmission control circuit can cause the inverter circuit to transmit the voltages or deactivate the inverter circuit based on a first control signal. The transmitter circuit can further include an idle circuit configured to transmit an idle voltage between the first and second voltages when there is no data transmission. The idle circuit may transmit the idle voltage based on a second control signal. The first and second control signals may be configured to only be active when the other is inactive.

A radio frequency module includes a first terminal, a second terminal, a third terminal, a first switching circuit, a bandpass filter, a first band elimination filter, and a first wiring conductor. The first switching circuit switches between a connection between a first switch terminal and a second switch terminal and a connection between the first switch terminal and a third switch terminal. The bandpass filter is disposed on a first signal path connecting the first terminal to the first switch terminal, and has a first passband. The first band elimination filter is disposed on a second signal path connecting the second switch terminal to the second terminal, and has a first elimination band included in the first passband. The first wiring conductor forms a third signal path connecting the third switch terminal to the third terminal.

A front-end circuit includes an antenna connection terminal, a selection terminal, and a selection terminal, a switching circuit including a common terminal and selection terminals, a receive filter configured to pass a radio-frequency signal in Band B, a signal path connecting the selection terminal and the selection terminal and including the receive filter, a signal path connecting the selection terminal and the selection terminal and defining and functioning as a bypass path without any filter, and a filter coupled between the antenna connection terminal and the common terminal and configured to pass a first frequency range group including Band B.

A radio frequency (RF) device includes a spatial orientation sensor and logic circuit configured to determine spatial orientation of the RF device relative to a reference position or relative to a RF transmitter. In particular, the RF device determines a distance between the RF receiver and the RF transmitter based on a received signal strength of the signal and a determined spatial orientation of the RF device, by determining an orientation compensation value from a stored orientation compensation profile and determining a resulting compensated received signal strength. The RF device is thereby able to determine distance in an orientationally-invariant manner.