H04B14/023

Method for determining an inverse impulse response of a communication channel

A method for determining an inverse impulse response of a communication channel by means of a PAM receiver comprises the following method steps: switching on the PAM receiver; if a second PAM transceiver is switched on, setting a difference between a clock frequency of the data signal and a sampling frequency of the first PAM transceiver; comparing a symbol that is output by the interpreter with a state that is supplied to the interpreter, and outputting an error value, wherein in each case a symbol associated with a sampling clock is compared with a state associated with the same sampling clock; adapting m filter coefficients of the equalizer to minimize error values; repeating the third method step and the fourth method step until an error limit value is reached.

METHOD FOR DETERMINING AN INVERSE IMPULSE RESPONSE OF A COMMUNICATION CHANNEL
20220407536 · 2022-12-22 ·

A method for determining an inverse impulse response of a communication channel by means of a PAM receiver comprises the following method steps: switching on the PAM receiver; if a second PAM transceiver is switched on, setting a difference between a clock frequency of the data signal and a sampling frequency of the first PAM transceiver; comparing a symbol that is output by the interpreter with a state that is supplied to the interpreter, and outputting an error value, wherein in each case a symbol associated with a sampling clock is compared with a state associated with the same sampling clock; adapting m filter coefficients of the equalizer to minimize error values; repeating the third method step and the fourth method step until an error limit value is reached.

MEMORY SYSTEM AND OPERATIONS OF THE SAME
20230059960 · 2023-02-23 ·

Methods, systems, and devices related to a memory system or scheme that includes a first memory device configured for low-energy access operations and a second memory device configured for storing high-density information and operations of the same are described. The memory system may include an array configured for high-density information and may interface with a host via a controller and a cache or another array of a relatively fast memory type. The memory system may support signals communicated according to one or several modulation schemes, including a modulation scheme or schemes that employ two, three, or more voltage levels (e.g., NRZ, PAM4). The memory system may include, e.g., separate channels configured to communicate using different modulation schemes between a host and between memory arrays or memory types within the memory system.

Multi-stage probabilistic signal shaping
11662645 · 2023-05-30 · ·

A shaping encoder capable of improving the performance of PCS in nonlinear optical channels by performing the shaping in two or more stages. In an example embodiment, a first stage employs a shaping code of a relatively short block length, which is typically beneficial for nonlinear optical channels but may cause a significant penalty in the energy efficiency. A second stage then employs a shaping code of a much larger block length, which significantly reduces or erases the penalty associated with the short block length of the first stage while providing an additional benefit of good performance in substantially linear optical channels. In at least some embodiments, the shaping encoder may have relatively low circuit-implementation complexity and/or relatively low cost and provide relatively high energy efficiency and relatively high shaping gain for a variety of optical channels, including but not limited to the legacy dispersion-managed fiber-optic links.

Receiver with threshold level finder
11646916 · 2023-05-09 · ·

An illustrative receiver includes: a decision element that derives symbol decisions from a slicer input signal; an equalizer that converts a receive signal into the slicer input signal; a summer that combines the symbol decisions with the slicer input signal to produce an error signal; and a level finder that operates on said signals to determine thresholds at which each signal has a given probability of exceeding the threshold. One illustrative level finder circuit includes: a gated comparator and an asymmetric accumulator. The gated comparator asserts a first or a second gated output signal to indicate when an input signal exceeds or falls below a threshold with a programmable condition being met. The asymmetric accumulator adapts the threshold using up steps for assertions of the first gated output signal and down steps for assertions of the second gated output signal, with the up-step size being different than the down-step size.

Data Processing Method and Data Processing Apparatus
20170310529 · 2017-10-26 ·

A data processing method and an apparatus, where the method includes receiving m data streams using m receive ports respectively, where the m data streams include m×m data units, and the m×m data units form an m-order matrix A, keeping a location of one element in each row in the matrix A unchanged and moving remaining m−1 elements to remaining m−1 rows respectively in order to form an m-order matrix B, where a column number of each element in the remaining m−1 elements in the matrix A before the element is moved equals a column number of the element in the remaining m−1 elements in the matrix B after the element is moved, and sending using m transmit ports, the m×m elements in the matrix B to m different levels of a pulse amplitude modulation (PAM) circuit respectively for performing modulation.

Memory system and operations of the same
11429291 · 2022-08-30 · ·

Methods, systems, and devices related to a memory system or scheme that includes a first memory device configured for low-energy access operations and a second memory device configured for storing high-density information and operations of the same are described. The memory system may include an array configured for high-density information and may interface with a host via a controller and a cache or another array of a relatively fast memory type. The memory system may support signals communicated according to one or several modulation schemes, including a modulation scheme or schemes that employ two, three, or more voltage levels (e.g., NRZ, PAM4). The memory system may include, e.g., separate channels configured to communicate using different modulation schemes between a host and between memory arrays or memory types within the memory system.

MULTI-LEVEL OUTPUT DRIVER WITH ADJUSTABLE PRE-DISTORTION CAPABILITY

A PAM (Pulse Amplitude Modulation) modulator driver is configured to receive a PAM input signal having N input amplitude levels and provide a PAM output signal having N output amplitude levels, where N is an integer. The PAM modulator driver circuit configured to electrically adjust amplitude levels in the PAM output signal.

PAM-4 calibration
11196595 · 2021-12-07 · ·

A hybrid voltage mode (VM) and current mode (CM) four-level pulse amplitude modulation (PAM-4) transmitter circuits (a.k.a. drivers) is calibrated using a configurable replica circuit and calibration control circuitry. The replica circuit includes an on-chip termination impedance to mimic a receiver's termination impedance. The amount of level enhancement provided by the current mode circuitry is calibrated by adjusting the current provided to the output node and sunk from the output node by the replica current mode circuitry while the replica voltage mode circuitry is driving an intermediate PAM-4 level. After the level enhancement has been set, the non-linearity between levels is calibrated by adjusting the amount of current provided to the output node by the replica current mode circuitry while the replica voltage mode circuitry is driving a maximum output voltage level.

Probabilistic signal shaping using multiple codebooks
11196594 · 2021-12-07 · ·

A communication system in which multiple shaping codes are selectively and iteratively used to encode a data frame such that possible energy inefficiencies associated with the use of constant-probability codes and/or transmission of dummy constellation symbols can be relatively small. In an example embodiment, the used shaping codes have different respective code rates, and a code selector of the shaping encoder operates to select one of the shaping codes by adaptively matching the rate of the code to the effective rate needed to efficiently encode the unprocessed portion of the data frame. The encoding is carried out in a manner that enables the shaping decoder to unequivocally determine the shaping codes that have been used for encoding each particular data frame based on the same rate-matching criteria as those used by the shaping encoder. At least some embodiments advantageously lend themselves to being implemented using circuits of relatively low complexity.