Duty cycles of pulse width modulation (“PWM”) pulses are determined by measurements taken with respect to an internally generated clock signal. One of these measurements calculates, in a continuous dynamic manner, a ratio of the number of cycles of the internally generated clock signal to one or more cycles of a PWM clock signal utilized as a time base for generation of the PWM pulses. This clock ratio measurement designates how many cycles of the internally generated clock signal will be used to designate a first portion of a duty cycle for each PWM pulse. Another measurement is utilized to determine a fractional portion of a cycle of the internally generated clock signal that will be used to designate a second portion of the duty cycle for each PWM pulse.

An amplifier circuit acting as a line driver in a line between a central station and field devices connected thereto comprising: a DC/DC converter integrated in the circuit as a power stage comprising a DC/pulse converter with two electrically isolated switching stages; a logic block preceding the converter, generating control signals for the switches from a PWM signal and feeding them into the converter in an electrically isolated manner using drivers; a priority block generating the PWM signal; a first and a second controller. The priority block forwards output from the first or second controller. The first controller generates a fault signal based on a voltage limit and an output voltage fed back within the amplifier circuit via a feedback path. The second controller generates a fault signal based on a current limit and the output current. The central station defines the current limit and the voltage limit.

A device includes a sensor configured to output an analog sensor signal, an analog-to-digital converter circuit configured to convert the analog sensor signal into a sigma-delta-modulated digital signal having a bit width of n bits, and a pulse width modulator configured to generate a pulse-width-modulated signal based on the sigma-delta-modulated digital signal.

A communication system is configured to use a pulse width modulation signal as transmission code among a plurality of nodes connected to a communication line. A master node includes a transmission transistor connected to the communication line, a detector configured to detect a variation in current during the on-period of the transmission transistor, and a communication circuit configured to determine the off-timing of the transmission transistor based on the timing of occurrence of the variation in current (i.e., the on-timing of a second transmission transistor provided in a slave node). For example, the communication circuit can be configured to determine the off-timing of the transmission transistor such that the simultaneously-on period TB of the transmission transistor and the second transmission transistor fulfills TB=(2n−1)/2f, where f is the frequency of EMI noise.

A decoding circuit and a chip are disclosed. The decoding circuit includes, connected in a sequence, a charge/discharge unit, a capacitor and a conversion unit. The charge/discharge unit is able to charge and discharge the capacitor, and a ratio of a total time required to transfer any amount of charge into the capacitor to a total time required to transfer the same amount of charge from the capacitor is a predetermined value. The conversion unit is configured to output a third level when a voltage on the capacitor exceeds a predetermined voltage and to otherwise output a fourth level. This arrangement alleviates the computational burden of an MCU, eliminates any adverse effect of noise in a transmitted signal, allows an extended effective transmission distance when using an HBS protocol and is self-adaptive to signals transmitted at different clock rates, thus solving the problems with the prior art including heavy MCU computational burden, a tradeoff between error correction and transmission distance and insufficient adaptiveness to signals transmitted at different clock rates.

A clock sending apparatus and method, and a clock receiving apparatus and method are disclosed. The clock sending apparatus may include, an input unit configured to input a first and second input clocks; a sampling unit configured to acquire a first and second sampling clocks, and determine a first frequency control word according to the first and second sampling clocks, the first frequency control word is indicative of a relationship between the first and second sampling clocks, the first sampling clock is determined by the first input clock according to a preset rule, and the second sampling clock is determined by the second input clock according to a preset rule; and a sending unit configured to generate a clock signal according to the first input clock and send the clock signal that carries at least the first frequency control word to a receiving side.

Methods, systems, and apparatuses for a single edge nibble transmission (SENT) multi-transmission mode are described. In an example, a system can include a transmitter and a receiver connected to one another. The transmitter may encode an identifier of a device in a synchronization nibble of a SENT signal. The transmitter may transmit the SENT signal with the encoded identifier to the receiver. The receiver may receive the SENT signal from the transmitter. The receiver may decode the identifier of the device from the synchronization nibble of the SENT signal to identify the device.

A decoding circuit and a chip are disclosed. The decoding circuit includes, connected in a sequence, a charge/discharge unit, a capacitor and a conversion unit. The charge/discharge unit is able to charge and discharge the capacitor, and a ratio of a total time required to transfer any amount of charge into the capacitor to a total time required to transfer the same amount of charge from the capacitor is a predetermined value. The conversion unit is configured to output a third level when a voltage on the capacitor exceeds a predetermined voltage and to otherwise output a fourth level. This arrangement alleviates the computational burden of an MCU, eliminates any adverse effect of noise in a transmitted signal, allows an extended effective transmission distance when using an HBS protocol and is self-adaptive to signals transmitted at different clock rates, thus solving the problems with the prior art including heavy MCU computational burden, a tradeoff between error correction and transmission distance and insufficient adaptiveness to signals transmitted at different clock rates.

A system and method is disclosed, to generate an AC signal having a positive and negative half-cycles, each comprising a plurality of PWM pulses each with an individually designated pulse width, the system comprising: a first clock circuit; a second, faster, clock circuit; clock ratio measurement circuitry configured to output a first measurement being a ratio of frequencies; a propagation delay circuit configured to measure a number of propagation elements through which a bit transition propagates within a second clock signal period; pulse data calculation element configured to determine pulse shaping data; and for each of the half-cycles, a respective pulse synthesis circuit configured to synthesise the respective plurality of PWM pulses, each pulse having a respective start defined by the first clock signal, and a pulse width defined by the pulse shaping data and synthesised from the second clock and an output pulse from the propagation delay circuit.

An illustrative receiver includes: a decision element that derives symbol decisions from a slicer input signal; an equalizer that converts a receive signal into the slicer input signal; a summer that combines the symbol decisions with the slicer input signal to produce an error signal; and a level finder that operates on said signals to determine thresholds at which each signal has a given probability of exceeding the threshold. One illustrative level finder circuit includes: a gated comparator and an asymmetric accumulator. The gated comparator asserts a first or a second gated output signal to indicate when an input signal exceeds or falls below a threshold with a programmable condition being met. The asymmetric accumulator adapts the threshold using up steps for assertions of the first gated output signal and down steps for assertions of the second gated output signal, with the up-step size being different than the down-step size.