The invention provides a system improving signal handling, e.g., transmission and/or processing. In an embodiment, the system may include a filter circuit, a magnitude bit truncation circuit and a utility circuit. The filter circuit may be coupled to a target signal which contains one or more desired signals at one or more interested bands, for attenuating each said interested band to form a filtered signal. The magnitude bit truncation circuit may be coupled to the filter circuit, for truncating one or more bits of each sample of the filtered signal to form a truncated signal. The utility circuit may be coupled to the magnitude bit truncation circuit, for handling the truncated signal to implement handling of the target signal, so as to reduce resource requirement and enhance error tolerance comparing with directly handling the target signal.

A cellular radio architecture that includes a multiplexer coupled to an antenna structure and including multiple signal paths, where each signal path includes a bandpass filter that passes a different frequency band than the other bandpass filters and a circulator that provides signal isolation between the transmit signals and the receive signals. The architecture also includes a receiver module having a separate signal channel for each of the signal paths in the multiplexer, where each signal channel in the receiver module includes a receiver delta-sigma modulator that converts analog receive signals to a representative digital signal. The delta-sigma modulator includes an LC filter having a plurality of LC resonator circuits, a plurality of transconductance amplifiers and a plurality of integrator circuits, where a combination of one resonator circuit, transconductance amplifier and integrator circuit represents a two-order stage of the LC filter.

A cellular radio architecture that includes a multiplexer coupled to an antenna structure and including multiple signal paths, where each signal path includes a bandpass filter that passes a different frequency band than the other bandpass filters and a circulator that provides signal isolation between the transmit signals and the receive signals. The architecture also includes a receiver module having a separate signal channel for each of the signal paths in the multiplexer, where each signal channel in the receiver module includes a receiver delta-sigma modulator that converts analog receive signals to a representative digital signal. The delta-sigma modulator includes an LC filter having a plurality of LC resonator circuits, a plurality of transconductance amplifiers and a plurality of integrator circuits, where a combination of one resonator circuit, transconductance amplifier and integrator circuit represents a two-order stage of the LC filter.

The present disclosure relates to a circuit including an input terminal configured to receive a first signal at a first frequency; a demodulation chain connected to the input terminal and including a low-noise amplifier having an input coupled to the terminal; a controllable variable impedance connected between a first node and a node configured to receive a reference potential, the first node being connected to the input terminal and/or to the amplifier input; and a current source configured to deliver a current at the first frequency to the first node.

The purpose of the present invention is to provide a high-power-efficiency and low-design-cost transmission device by implementing, with a constant clock, delta-sigma modulation maintaining a zero current switching property in an amplifier. This delta-sigma modulator comprises: a pulse phase signal generation unit for generating a pulse phase signal from a phase signal; a delta-sigma modulation unit for generating a pulse amplitude signal obtained by delta-sigma modulating an amplitude signal with a constant clock; a phase sorting unit for outputting a control signal on the basis of the phase signal; a delay switching unit for delaying the pulse amplitude signal on the basis of the control signal; and a mixing unit for outputting a pulse string obtained by multiplying together the delayed pulse amplitude signal and the pulse phase signal.

A data communication method in which input digital data is received and encoded into an encoded waveform having zero crossings representative of the input digital data. The encoding includes generating the encoded waveform based upon a continuous piecewise function having sinusoidal components. The continuous piecewise function may be used in generating a plurality of symbol waveforms, each of which occupies a period of the encoded waveform and represents bits of the input digital data. The plurality of symbol waveforms are defined so that a value of a phase offset used in the continuous piecewise function is different for each of the plurality of symbol waveforms, thereby resulting in each symbol waveform having a different zero crossing. An encoded analog waveform is generated from a representation of the encoded waveform and transmitted to a receiver.

A data communication method in which input digital data is received and encoded into an encoded waveform having zero crossings representative of the input digital data. The encoding includes generating the encoded waveform based upon a continuous piecewise function having sinusoidal components. The continuous piecewise function may be used in generating a plurality of symbol waveforms, each of which occupies a period of the encoded waveform and represents bits of the input digital data. The plurality of symbol waveforms are defined so that a value of a phase offset used in the continuous piecewise function is different for each of the plurality of symbol waveforms, thereby resulting in each symbol waveform having a different zero crossing. An encoded analog waveform is generated from a representation of the encoded waveform and transmitted to a receiver.

A method of recovering information encoded by a modulated sinusoidal waveform having first, second, third and fourth data notches at respective phase angles, where a power of the modulated sinusoidal waveform is reduced relative to a power of an unmodulated sinusoidal waveform within selected ones of the first, second, third and fourth data notches so as to encode input digital data. The method includes receiving the modulated sinusoidal waveform and generating digital values representing the modulated sinusoidal waveform. A digital representation of the unmodulated sinusoidal waveform is subtracted from the digital values in order to generate a received digital data sequence, which includes digital data notch values representative of the amplitude of the modulated sinusoidal waveform within the first, second, third and fourth data notches. The input digital data is then estimated based upon the digital data notch values.

A method of recovering information encoded by a modulated sinusoidal waveform having first, second, third and fourth data notches at respective phase angles, where a power of the modulated sinusoidal waveform is reduced relative to a power of an unmodulated sinusoidal waveform within selected ones of the first, second, third and fourth data notches so as to encode input digital data. The method includes receiving the modulated sinusoidal waveform and generating digital values representing the modulated sinusoidal waveform. A digital representation of the unmodulated sinusoidal waveform is subtracted from the digital values in order to generate a received digital data sequence, which includes digital data notch values representative of the amplitude of the modulated sinusoidal waveform within the first, second, third and fourth data notches. The input digital data is then estimated based upon the digital data notch values.

The present application relates to a wave limiting circuit, and a pre-calibration method, a dynamic correction method and apparatuses therefor. The circuit comprises: an LC series resonance circuit, a controller and a matching element, wherein a first end of the matching element is connected to a radio frequency circuit; a second end thereof is connected to an antenna, and a third end thereof is connected to one end of the LC series resonance circuit; and the other end of the LC series resonance circuit is connected to the controller so as to adjust parameters of the LC series resonance circuit by means of the controller.