A frequency equalizer is provided. The frequency equalizer includes a coupler including a main segment extending between a first port and a second port and a coupled segment disposed in a coupling relationship with the main segment and extending between a third port and a fourth port. The frequency equalizer further includes a first thermistor electrically coupled in series between the first port and an input line, a second thermistor electrically coupled in series between the second port and an output line, and a first shunt resistor coupled across the third port. The frequency equalizer simultaneously provides frequency equalization and temperature compensation for signals transmitted through the frequency equalizer.

A frequency equalizer is provided. The frequency equalizer includes a coupler including a main segment extending between a first port and a second port and a coupled segment disposed in a coupling relationship with the main segment and extending between a third port and a fourth port. The frequency equalizer further includes a first thermistor electrically coupled in series between the first port and an input line, a second thermistor electrically coupled in series between the second port and an output line, and a first shunt resistor coupled across the third port. The frequency equalizer simultaneously provides frequency equalization and temperature compensation for signals transmitted through the frequency equalizer.

A cable equalizer configured as part of a cable comprising a first stage, a second stage, and a third stage. The first stage comprises a first stage bias current circuit configured to generate a bias current and a pre-emphasis module configured to introduce pre-emphasis into a received signal to counter the effects of signal amplification. Also part of the first stage is a bias voltage circuit configured to provide a bias voltage to the first stage. The second stage comprises a buffer configured impedance match the first stage. The third stage comprises a third stage bias current circuit configured to generate a bias current and a tank equalizer circuit configured to perform frequency specific equalization on a second stage signal. An amplifier is configured to amplify the second stage signal to create an amplified signal, which is output from the cable equalizer by an output driver.

In order to achieve impedance matching, a connector (A) is provided with: a housing (10) having terminal receiving chambers (11) disposed in two rows; two short-circuit members (30) which are attached to a plurality of terminal receiving chambers (11) arrayed in one row and a plurality of terminal receiving chambers (11) arrayed in the other row, and which constitute a differential pair; a plurality of terminal fixtures (40) which are separately fixedly attached to a main line (51) constituting the differential pair and a sub-line (52) constituting the differential pair, and which are inserted into the terminal receiving chambers (11) and are thereby connected to the short-circuit members (30); and a plurality of lances (13) formed on the housing (10) to prevent removal of the terminal fixtures (40) inserted into the terminal receiving chambers (11). The lances (13) are only provided in regions different from a region sandwiched between the plurality of terminal receiving chambers (11) arrayed in one row and the plurality of terminal receiving chambers (11) arrayed in the other row.

Methods and systems are described for receiving symbols of a codeword via wires of a multi-wire bus, the codeword representing an aggregate sum of a plurality of sub-channel constituent codewords, each sub-channel constituent codeword representing a weight applied to an associated sub-channel vector of a plurality of sub-channel vectors of an orthogonal matrix, generating a plurality of comparator outputs using a plurality of common-mode resistant multi-input comparators (MICs), each common-mode resistant MIC having a set of input coefficients representing a corresponding sub-channel vector of the plurality of sub-channel vectors, each sub-channel vector (i) mutually orthogonal and (ii) orthogonal to a common-mode sub-channel vector, outputting a set of forward-channel output bits formed based on the plurality of comparator outputs, obtaining a sequence of reverse-channel bits, and transmitting the sequence of reverse-channel bits by sequentially transmitting common-mode codewords over the wires of the multi-wire bus.

Methods and systems are described for receiving symbols of a codeword via wires of a multi-wire bus, the codeword representing an aggregate sum of a plurality of sub-channel constituent codewords, each sub-channel constituent codeword representing a weight applied to an associated sub-channel vector of a plurality of sub-channel vectors of an orthogonal matrix, generating a plurality of comparator outputs using a plurality of common-mode resistant multi-input comparators (MICs), each common-mode resistant MIC having a set of input coefficients representing a corresponding sub-channel vector of the plurality of sub-channel vectors, each sub-channel vector (i) mutually orthogonal and (ii) orthogonal to a common-mode sub-channel vector, outputting a set of forward-channel output bits formed based on the plurality of comparator outputs, obtaining a sequence of reverse-channel bits, and transmitting the sequence of reverse-channel bits by sequentially transmitting common-mode codewords over the wires of the multi-wire bus.

A physical layer transceiver for a data channel includes receiver circuitry configured to receive signals on the data channel, transmit circuitry configured to transmit signals onto the data channel, and adaptive filter circuitry coupled to the receiver circuitry and the transmit circuitry and configured to filter the data channel by operating on input frequency-domain data samples to output filtered data samples. The adaptive filter circuitry includes error sample generation circuitry configured to generate error samples representing a difference between a target response and the filtered data samples, arithmetic-only circuitry configured to approximate a windowing function to operate on the error samples, and output sample generation circuitry configured to operate on windowed error samples to provide the output filtered data samples. The comparison circuitry may be configured for time-domain operation and may further be configured to transform the error signals into frequency-domain error signals.

An integrated circuit equalizes a data signal expressed as a series of symbols. The symbols form data patterns with different frequency components. By considering these patterns, the integrated circuit can experiment with equalization settings specific to a subset of the frequency components, thereby finding an equalization control setting that optimizes equalization. Optimization can be accomplished by setting the equalizer to maximize symbol amplitude.

Methods and systems are described for receiving symbols of a codeword via wires of a multi-wire bus, the codeword representing an aggregate sum of a plurality of sub-channel constituent codewords, each sub-channel constituent codeword representing a weight applied to an associated sub-channel vector of a plurality of sub-channel vectors of an orthogonal matrix, generating a plurality of comparator outputs using a plurality of common-mode resistant multi-input comparators (MICs), each common-mode resistant MIC having a set of input coefficients representing a corresponding sub-channel vector of the plurality of sub-channel vectors, each sub-channel vector (i) mutually orthogonal and (ii) orthogonal to a common-mode sub-channel vector, outputting a set of forward-channel output bits formed based on the plurality of comparator outputs, obtaining a sequence of reverse-channel bits, and transmitting the sequence of reverse-channel bits by sequentially transmitting common-mode codewords over the wires of the multi-wire bus.

Methods and systems are described for receiving symbols of a codeword via wires of a multi-wire bus, the codeword representing an aggregate sum of a plurality of sub-channel constituent codewords, each sub-channel constituent codeword representing a weight applied to an associated sub-channel vector of a plurality of sub-channel vectors of an orthogonal matrix, generating a plurality of comparator outputs using a plurality of common-mode resistant multi-input comparators (MICs), each common-mode resistant MIC having a set of input coefficients representing a corresponding sub-channel vector of the plurality of sub-channel vectors, each sub-channel vector (i) mutually orthogonal and (ii) orthogonal to a common-mode sub-channel vector, outputting a set of forward-channel output bits formed based on the plurality of comparator outputs, obtaining a sequence of reverse-channel bits, and transmitting the sequence of reverse-channel bits by sequentially transmitting common-mode codewords over the wires of the multi-wire bus.