Methods, systems, and devices for techniques for enabling and disabling of a serializer/deserializer are described. In some examples, a system may be configured to identify information to be transmitted by a serializer/deserializer over a communication channel and activate, based on identifying the information to be transmitted, both a transmission component and a reception component of the serializer/deserializer that are coupled with the communication channel. Additionally or alternatively, in some examples, a system may be configured to identify information to be received by a serializer/deserializer over a communication channel and activate, based on identifying the information to be received, both a transmission component and a reception component of the serializer/deserializer that are coupled with the communication channel.

A multiplexer selects one of a first to a fourth data signal in response to a first to a fourth pulse. The first to fourth pulses respectively correspond to the first to fourth data signals and sequentially toggle. The multiplexer includes: (1) a NAND gate that receives the first data signal, a fourth complementary data signal that is a complementary signal of the fourth data signal, and the first pulse and outputs a first gate signal and (2) a NOR gate that receives the first data signal, the fourth complementary data signal, and a first complementary pulse that is complementary to the first pulse and outputs a second gate signal. The first data signal corresponds to a rising edge of the first pulse, and the fourth complementary data signal corresponds to a rising edge of the fourth pulse.

A multiplexer selects one of a first to a fourth data signal in response to a first to a fourth pulse. The first to fourth pulses respectively correspond to the first to fourth data signals and sequentially toggle. The multiplexer includes: (1) a NAND gate that receives the first data signal, a fourth complementary data signal that is a complementary signal of the fourth data signal, and the first pulse and outputs a first gate signal and (2) a NOR gate that receives the first data signal, the fourth complementary data signal, and a first complementary pulse that is complementary to the first pulse and outputs a second gate signal. The first data signal corresponds to a rising edge of the first pulse, and the fourth complementary data signal corresponds to a rising edge of the fourth pulse.

A serial link interface unit includes serialized data stream interfaces configured to receive a serialized data stream having a data rate and set of timeslots; an aggregate serialized data stream interface configured to communicate an aggregate serialized data stream having aggregate data rate and plurality of aggregate timeslot sets each coming sequentially in time, wherein a second aggregate timeslot set comes after a first aggregate timeslot set; and wherein the serial link interface unit interleaves data from the different serialized data streams received at the plurality of first interfaces by mapping data from a first timeslot from each different serialized data stream to the first aggregate timeslot set in the aggregate serialized data stream and mapping data from a second timeslot from each different serialized data stream to the second aggregate timeslot set in the aggregate serialized data stream.

A serial link interface unit includes serialized data stream interfaces configured to receive a serialized data stream having a data rate and set of timeslots; an aggregate serialized data stream interface configured to communicate an aggregate serialized data stream having aggregate data rate and plurality of aggregate timeslot sets each coming sequentially in time, wherein a second aggregate timeslot set comes after a first aggregate timeslot set; and wherein the serial link interface unit interleaves data from the different serialized data streams received at the plurality of first interfaces by mapping data from a first timeslot from each different serialized data stream to the first aggregate timeslot set in the aggregate serialized data stream and mapping data from a second timeslot from each different serialized data stream to the second aggregate timeslot set in the aggregate serialized data stream.

A summing unit within telecommunications system includes: port to receive digital data stream from another device; and summer function. Digital data stream includes first and second digital data derived from first and second base station. First and second digital data comprises first and second digital values associated with respective time periods. Summing unit extracts first digital data from digital data stream. Summer function digitally sums first digital data with third digital data derived from third base station to generate summed digital data for conversion to radio frequency signals and transmission at antenna. Third digital data comprises third series of third digital values associated with respective time periods. Summer function digitally sums first digital data with third digital data by digitally summing (i) first digital value associated with respective time period and (ii) third digital value associated with respective time period to produce summed value for respective time period.

A summing unit within telecommunications system includes: port to receive digital data stream from another device; and summer function. Digital data stream includes first and second digital data derived from first and second base station. First and second digital data comprises first and second digital values associated with respective time periods. Summing unit extracts first digital data from digital data stream. Summer function digitally sums first digital data with third digital data derived from third base station to generate summed digital data for conversion to radio frequency signals and transmission at antenna. Third digital data comprises third series of third digital values associated with respective time periods. Summer function digitally sums first digital data with third digital data by digitally summing (i) first digital value associated with respective time period and (ii) third digital value associated with respective time period to produce summed value for respective time period.

In some implementations, a communication device, includes a printed circuit board comprising conductors routed to support a plurality of different configurations of modulation and/or demodulation functionality. The printed circuit board can have multiple analog output interfaces and one or more analog input interfaces, multiple digital network interfaces, and sockets for components including a controller, multiple processors, digital-to-analog converters (DACs), and an analog-to-digital converter (ADC). Various processor sockets are interconnected to support the processors in different sockets selectively being used for different functions, e.g., as a modulator, burst processor, channelizer, etc.

A transmit driver architecture with a test mode (e.g., a JTAG configuration mode), extended equalization range, and/or multiple power supply domains. One example transmit driver circuit generally includes one or more driver unit cells having a differential input node pair configured to receive an input data signal and having a differential output node pair configured to output an output data signal; a plurality of power switches coupled between the differential output node pair and one or more power supply rails; a first set of one or more drivers coupled between a first test node of a differential test data path and a first output node of the differential output node pair; and a second set of one or more drivers coupled between a second test node of the differential test data path and a second output node of the differential output node pair.

A multi-chip module (MCM) may include a substrate, and first and second physical-layer (PHY) chips mounted on the substrate. In some implementations, the first PHY chip includes a multiplexer and a PHY circuit. The multiplexer is configured to receive a multiplexed data stream from a media access control (MAC) device, to demultiplex the multiplexed data stream into first and second data streams, to output the first data stream to the PHY circuit, and to output the second data stream to the second PHY chip. In some implementations, the first PHY includes a router and a PHY circuit. The router is configured to receive a plurality of data packets from a MAC device, to route one or more of the data packets having a first address to the PHY circuit, and to route one or more of the data packets having a second address to the second PHY chip.