Patent classifications
H04J3/062
ETHERNET INTERFACE AND RELATED SYSTEMS METHODS AND DEVICES
Described is a digital interface and related systems, method and devices. In some embodiments, an interface may be an interface between a link layer and a physical transmission medium. The interface may be configured for a bit rate and/or reference clock that limits electromagnetic emissions (EME), for example, as compared to a bit rate and/or clock rate specified by interfaces widely used in industry.
MISSING DATA PACKET COMPENSATION
Methods of compensating for lost data packets in hearing aid systems wherein a data streaming device streams packets of data to at least two hearing aids are disclosed.
Ethernet interface and related systems methods and devices
Described is a digital interface and related systems, method and devices. In some embodiments an interface may be an interface between a link layer and a physical transmission medium. The interface may be configured for a bit rate and/or reference clock that limits electromagnetic emissions (EME), for example as compared to a bit rate and/or clock rate specified by interfaces widely used in industry.
Diagnostic System and Method for Network Synchronized Time in Safety Applications
To improve integrity of time synchronization, a node in a safety rated system verifies that its clock remains synchronized to another clock. Two adjacent, time-synchronized nodes transmit diagnostic messages to each other at an agreed upon interval and generate timestamps when the diagnostic message is received from the other node. The nodes then transmit their respective timestamp back to the sending node. Clock drift is detected by comparing a difference between the two timestamps at which the messages were received against a threshold. To avoid accidental detection of clock drift, a difference in transmission delays between the two nodes is stored in a FIFO buffer. Each node monitors the average of the data in the FIFO buffer. If the average deviates from the target value by too great a value, then the node determines the values of the clocks have skewed beyond an acceptable range and generates a fault condition.
Ethernet interface and related systems, methods and devices
Described is a digital interface and related systems, method and devices. In some embodiments, an interface may be an interface between a link layer and a physical transmission medium. The interface may be configured for a bit rate and/or reference clock that limits electromagnetic emissions (EME), for example, as compared to a bit rate and/or clock rate specified by interfaces widely used in industry.
TRANSMISSION APPARATUS AND TRANSMISSION SYSTEM
A first reception processing unit performs a process of receiving a first signal transmitted on a first transmission line, a second reception processing unit performs a process of receiving a second signal transmitted on a second transmission line, and an output speed control unit controls output speeds of the first signal and the second signal subjected to the reception process. A system switching unit selects and outputs the first signal or the second signal subjected to a reception process, and an output processing unit performs a process for output to another apparatus on the output from the system switching unit. A reception side clock output unit outputs a clock signal giving a processing timing of each process, and a clock frequency control unit adjusts a frequency of the clock signal giving the processing timing to the output processing unit. A frequency adjustment range calculation unit calculates an adjustment range of the frequency based on frequency deviation accuracy of the reception side clock output unit, frequency deviation accuracy of a transmission side clock output unit that outputs a clock signal giving a processing timing to a transmission process at a transmission apparatus on the transmission side, and a prescribed value of a frequency deviation.
Digitally programmable analog duty-cycle correction circuit
Various aspects provide for a digitally programmable analog duty-cycle correction circuit. For example, a system includes a duty-cycle correction circuit and a duty-cycle distortion detector circuit. The duty-cycle correction circuit adjusts a clock associated with the transmitter. The duty-cycle distortion detector circuit facilitates digital control of a duty-cycle of the clock associated with the duty-cycle correction circuit based on duty-cycle distortion error associated with output of the transmitter.
TRANSMISSION DEVICE, TRANSMISSION METHOD, AND PROGRAM
Techniques for wireless transmission of data are provided, in which data representing a plurality of frames of a time-sequential signal are encoded. The encoded data are temporarily retained in a memory buffer before wireless transmission. A current number of frames of the encoded data awaiting transmission is determined, and a compression rate is selected for encoding the next frame of data of the time-sequential signal based on the determined number of stored frames in the memory buffer. The selected compression rate is used to encode the next frame of the time-sequential signal, which is added to the encoded data stored in the memory buffer and wirelessly transmitted from the memory buffer. The present disclosure is applicable to a smartphone and a portable player, for example.
DIGITALLY PROGRAMMABLE ANALOG DUTY-CYCLE CORRECTION CIRCUIT
Various aspects provide for a digitally programmable analog duty-cycle correction circuit. For example, a system includes a duty-cycle correction circuit and a duty-cycle distortion detector circuit. The duty-cycle correction circuit adjusts a clock associated with the transmitter. The duty-cycle distortion detector circuit facilitates digital control of a duty-cycle of the clock associated with the duty-cycle correction circuit based on duty-cycle distortion error associated with output of the transmitter.
Transmission device, transmission method, and program
Techniques for wireless transmission of data are provided, in which data representing a plurality of frames of a time-sequential signal are encoded. The encoded data are temporarily retained in a memory buffer before wireless transmission. A current number of frames of the encoded data awaiting transmission is determined, and a compression rate is selected for encoding the next frame of data of the time-sequential signal based on the determined number of stored frames in the memory buffer. The selected compression rate is used to encode the next frame of the time-sequential signal, which is added to the encoded data stored in the memory buffer and wirelessly transmitted from the memory buffer. The present disclosure is applicable to a smartphone and a portable player, for example.