A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.

Generating, during a first and second signaling interval, an aggregated data signal by forming a linear combination of wire signals received in parallel from wires of a multi-wire bus, wherein at least some of the wire signals undergo a signal level transition during the first and second signaling interval; measuring a signal skew characteristic of the aggregated data signal; and, generating wire-specific skew offset metrics, each wire-specific skew offset metric based on the signal skew characteristic.

A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.

Various examples are directed to systems and methods for wideband digital predistortion. A digital pre-distortion circuit may be programmed to receive a complex baseband signal and generate a pre-distorted signal. Generating the pre-distorted signal may comprise applying to the complex baseband signal a first correction for an N.sup.th order distortion of a power amplifier at an I.sup.th harmonic frequency zone centered at about an I.sup.th harmonic of a carrier frequency and applying to the complex baseband signal a second correction for the N.sup.th order distortion at a J.sup.th harmonic frequency zone centered at about a J.sup.th harmonic of the carrier frequency different than the I.sup.th harmonic of a carrier frequency.

An improved receiver design implements a method for modeling users in SIC turbo loop multiuser detection architectures that reduces the number of implementation cycles, and thereby reduces the computational overhead associated with computing the inverse of the received signal covariance matrix, by efficiently reusing components of a QR decomposition. By reusing some of the computational results from the previous turbo loop's equalizer calculation, the disclosed receiver significantly reduces the computational burden of updating the linear equalizer on each turbo loop. Depending on the embodiment, this reduction can be accomplished in at least two different ways, depending on the dimensionality and other aspects of the implementation.

A transmitter for transmitting an output signal includes first and second filter structures. The first filter structure includes a first combiner to extend a first data signal by a first reference signal to obtain a first extended data signal, and a first IIR filter for filtering the first extended data signal to obtain a first filtered data signal. The second filter structure includes a second combiner to extend a second data signal by a second reference signal, and a second IIR filter for filtering the second extended data signal. The transmitter includes a multiplexer for combining the first and second filtered data signals to obtain the output signal. A system response of the first IIR filter based on the first reference signal corresponds to a system response of the second IIR filter based on the second reference signal.

Generating, during a first and second signaling interval, an aggregated data signal by forming a linear combination of wire signals received in parallel from wires of a multi-wire bus, wherein at least some of the wire signals undergo a signal level transition during the first and second signaling interval; measuring a signal skew characteristic of the aggregated data signal; and, generating wire-specific skew offset metrics, each wire-specific skew offset metric based on the signal skew characteristic.

Generating, during a first and second signaling interval, an aggregated data signal by forming a linear combination of wire signals received in parallel from wires of a multi-wire bus, wherein at least some of the wire signals undergo a signal level transition during the first and second signaling interval; measuring a signal skew characteristic of the aggregated data signal; and, generating wire-specific skew offset metrics, each wire-specific skew offset metric based on the signal skew characteristic.

Generating, during a first and second signaling interval, an aggregated data signal by forming a linear combination of wire signals received in parallel from wires of a multi-wire bus, wherein at least some of the wire signals undergo a signal level transition during the first and second signaling interval; measuring a signal skew characteristic of the aggregated data signal; and, generating wire-specific skew offset metrics, each wire-specific skew offset metric based on the signal skew characteristic.

Methods, systems are provided for reconfiguring the position of a first tap in a descrambler circuit LFSR after the LFSR has been trained and synchronized with a corresponding scrambler circuit LFSR. A data path from the second tap position to the descrambler output by-passes logic elements located in the data path from the first tap to the descrambler output, thereby reducing delay in the descrambler circuit after the reconfiguration (i.e., the “lock-shift” operation). The tap position change may be communicated by a mode manager to a corresponding scrambler circuit, for applying a matching reconfiguration in the scrambler circuit, either directly via an I/O line or indirectly. The indirect route includes in-band transmissions between two ICs with two sets of self-synchronizing scrambler/descrambler pairs, and is based on monitored receiver LFSR output signals that indicate when a scrambler/descrambler pair is synchronized or whether the output of a descrambler circuit comprises descrambled data.