Equalization circuitry for a data channel in an integrated circuit device includes an analog equalization stage coupled to the data channel, and a digital signal processing stage downstream of the analog equalization stage. The digital signal processing stage generates control signals to control the analog equalization stage, and includes a digital equalization stage that operates on output of the analog equalization stage. The analog equalization stage may further include an enhanced processing stage for optical signals, which may be selectably coupled to the analog equalization stage. The analog equalization stage may include at least one feed-forward or feedback equalization stage, and a decision stage that outputs decision signals at one of a first plurality of signal levels. The enhanced processing stage operates on the decision signals to output enhanced decision signals at one of a second plurality of signal levels of higher resolution than the first plurality of signal levels.

There is provided a method of receiving a transmitted signal over a time-varying channel. The method includes: obtaining a received symbol signal in frequency domain based on the transmitted signal; performing a first channel estimation based on the received symbol signal to obtain a plurality of first estimated BEM coefficients; performing a first equalization based on the received symbol signal and the plurality of first estimated BEM coefficients to obtain a plurality of first detected source symbols; and performing one or more rounds of a second channel estimation and a second equalization. Each round includes: performing the second channel estimation based on the received symbol signal and a plurality of detected source symbols to obtain a plurality of second estimated BEM coefficients; performing interference removal based on the received symbol signal, the plurality of detected source symbols and the plurality of second estimated BEM coefficients to obtain an interference reduced symbol signal infrequency domain; and performing the second equalization based on the interference reduced symbol signal and the plurality of second estimated BEM coefficients to obtain a plurality of second detected source symbols. There is also provided a corresponding receiver, and a system for wireless communication over a time-varying channel including the receiver.

The present disclosure relates to a pre-5th-generation (5G) or 5G communication system to be provided for supporting higher data rates beyond 4th-generation (4G) communication system such as a long term evolution (LTE). A method for receiving data includes selecting one of reception schemes, and receiving data based on the selected reception scheme, wherein the reception schemes includes a scheme of determining an integer matrix based on channel values estimated for channels, and decoding symbols received through the channels based on the determined integer matrix, and a scheme of detecting, for each channel, a sum of symbols received from each of the channels during a preset time based on integer matrixes which are determined based on each of the channel values, retransforming the sum of the symbols detected for each channel based on at least one of the integer matrixes, and decoding the retransformed sum of the symbols for each channel.

Example operations may include obtaining a first received signal of a first wireless transmission by a transmitting device of a wireless signal received at a receiving device. The operations may also include obtaining a second received signal of a second wireless transmission by the transmitting device that is a retransmission of the wireless signal also received at the receiving device. The operations may further include determining, based on the first received signal and the second received signal, an equalization of distortion of propagation of the wireless signal between the transmitting device and the receiving device. In addition, the operations may include generating an equalized signal based on the determined signal equalization, wherein the equalized signal is an estimate of the wireless signal as transmitted by the transmitting device.

A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

A low power receiver having a feedforward equalization, FFE, based continuous time linear equalizer, CTLE. The FFE CTLE comprises: an input for receiving an input signal; a main first path operably coupled to the input and comprising a source-follower transistor arranged to apply a scaling factor to the received input signal; a second path operably coupled to the input and comprising a delay arranged to apply a delay to the received input signal and a common source transistor common source transistor arranged to apply a scaling factor to the received delayed input signal, wherein the source-follower transistor and the common source, CS, transistor are connected as a single SF-CS stage whose output is arranged to subtract the output of the common source transistor from an output of the source-follower transistor.

A low power receiver having a feedforward equalization, FFE, based continuous time linear equalizer, CTLE. The FFE CTLE comprises: an input for receiving an input signal; a main first path operably coupled to the input and comprising a source-follower transistor arranged to apply a scaling factor to the received input signal; a second path operably coupled to the input and comprising a delay arranged to apply a delay to the received input signal and a common source transistor common source transistor arranged to apply a scaling factor to the received delayed input signal, wherein the source-follower transistor and the common source, CS, transistor are connected as a single SF-CS stage whose output is arranged to subtract the output of the common source transistor from an output of the source-follower transistor.

A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

Example operations may include obtaining a first received signal of a first wireless transmission by a transmitting device of a wireless signal received at a receiving device. The operations may also include obtaining a second received signal of a second wireless transmission by the transmitting device that is a retransmission of the wireless signal also received at the receiving device. The operations may further include determining, based on the first received signal and the second received signal, an equalization of distortion of propagation of the wireless signal between the transmitting device and the receiving device. In addition, the operations may include generating an equalized signal based on the determined signal equalization, wherein the equalized signal is an estimate of the wireless signal as transmitted by the transmitting device.

A wireless communication device is described. The wireless communication device includes a receiver. The receiver is configured to determine a time-domain sample of a single carrier based on a received signal. The receiver is also configured to determine an estimated value based on the time-domain sample. The receiver is further configured to perform slicing based on the estimated value to produce a sliced value. The receiver is additionally configured to adapt a frequency-domain coefficient based on the estimated value and the sliced value. The receiver is also configured to perform channel equalization based on the frequency-domain coefficient.