A wireless communication system includes a channel estimation circuit, a shortening circuit, a time-domain decision feedback equalizer and a coefficient calculation circuit. The channel estimation circuit generates an estimated channel pulse response according to a received signal. The shortening circuit defines a shortened impulse response from the estimated channel impulse response according to a main energy distribution region of the estimated channel impulse response. The time-domain decision feedback equalizer performs time-domain equalization on the received signal, and includes a feedforward filter for filtering the received signal. The coefficient calculation circuit calculates, according to the shortened impulse response, a set of feed-forward filter coefficients to be utilized by the feedforward filter.

Decision feedback equalization (DFE) taps and related apparatuses and methods are disclosed. An apparatus includes a first electrically controllable switch, a second electrically controllable switch, and one or more delay elements. The first electrically controllable switch receives a history bit and selectively provides the history bit to gate terminals of first transistors of a DFE tap circuitry. The second electrically controllable switch receives a complementary history bit and selectively provides the complementary history bit to second gate terminals of second transistors of the DFE tap circuitry. The one or more delay elements provide one or more delayed data integration clock signals responsive to one or more data integration clock signals. A complementary delayed data integration clock signal controls switching of the first electrically controllable switch and the second electrically controllable switch.

Transceivers and methods able to recover within less than 1 millisecond from quality degradation in the transceiver's operating point, including: receiving a signal from a second transceiver, using an adaptive digital equalizer and canceller (ADEC) to generate a slicer input signal, and generating slicing decisions and slicing errors that are used to adapt the ADEC. Shortly after identifying quality degradation in the transceiver's operating point, indicating the second transceiver to transmitting known data. And within less than 1 millisecond from identifying the quality degradation, the transceiver utilizes the known data to improve the accuracy of the slicing errors, which enables fast adaptation of the ADEC that improves the quality in the transceiver's operating point to a level that enables the transceiver to indicate the second transceiver to transmit data.

Generating first and second discharge control signals in response to a clock signal and an input voltage signal, the first and second discharge control signals decreasing at different rates to a threshold level during a first time period, wherein a difference in rates is determined by the input voltage signal, generating a differential voltage on a pair of nodes during the first time period by selectively controlling a respective amount of discharge of an initial charge on each node of the pair of nodes by applying the first and second discharge control signals to respective transistors in a differential transistor pair connected to the pair of nodes, and maintaining the differential voltage on the pair of nodes during a subsequent time period, and generating an amplified differential voltage during at least a portion of the subsequent time period by amplifying the differential voltage.

The present invention is directed to electrical circuits. More specifically, embodiments of the presentation provide a CTLE module that includes a two compensation sections. A high-frequency zero RC section is in the source of the differential pair and close to the bias current source. A low-frequency zero section is coupled to an output terminal and configured outside the input signal path. A DC gain tuning section is coupled to the low-frequency zero section. There are other embodiments as well.

It is difficult to obtain a demodulated signal with high signal quality in a digital optical receiver because it is difficult to compensate for each of different types of waveform distortion by a high-performance equalization process; therefore, a digital signal processor according to an exemplary aspect of the present invention includes a fixed equalization means for performing a distortion compensation process based on a fixed equalization coefficient on an input digital signal; an adaptive equalization means for performing an adaptive distortion compensation process based on an adaptive equalization coefficient on an equalized digital signal output by the fixed equalization means; a low-speed signal generation means for generating a low-speed digital signal by intermittently extracting one of the input digital signal and the equalized digital signal; a low-speed equalization coefficient calculation means for calculating a low-speed equalization coefficient to be used for a distortion compensation process of the low-speed digital signal; and a fixed equalization coefficient calculation means for calculating the fixed equalization coefficient by using at least a predetermined coefficient out of the low-speed equalization coefficient and the predetermined coefficient.

The present invention is directed to electrical circuits. More specifically, embodiments of the presentation provide a CTLE module that includes a two compensation sections. A high-frequency zero RC section is in the source of the differential pair and close to the bias current source. A low-frequency zero section is coupled to an output terminal and configured outside the input signal path. A DC gain tuning section is coupled to the low-frequency zero section. There are other embodiments as well.

A transceiver and a corresponding method configured to recover within less than 1 ms from quality degradation in its operating point. The transceiver includes: a receiver analog front end (Rx AFE), an adaptive module comprising at least one of an adaptive digital equalizer and an adaptive digital canceller (ADEC), a common mode sensor AFE (CMS-AFE), a fast-adaptive mode-conversion canceller (FA-MCC), and a slicer. The Rx AFE receives signals from a second transceiver. Shortly after identifying quality degradation in the transceiver's operating point, the transceiver indicates the second transceiver to reduce the rate of the transmitted data. And within less than 1 ms, the transceiver utilizes the improved detection rate to improve the accuracy of the slicing errors, which enables fast adaptation of the ADEC, that improves the quality in the transceiver's operating point to a level that enables the transceiver to indicate the second transceiver to increase the rate.

The present invention is directed to electrical circuits. More specifically, embodiments of the presentation provide a CTLE module that includes a two compensation sections. A high-frequency zero RC section is in the source of the differential pair and close to the bias current source. A low-frequency zero section is coupled to an output terminal and configured outside the input signal path. A DC gain tuning section is coupled to the low-frequency zero section. There are other embodiments as well.

Generating first and second discharge control signals in response to a clock signal and an input voltage signal, the first and second discharge control signals decreasing at different rates to a threshold level during a first time period, wherein a difference in rates is determined by the input voltage signal, generating a differential voltage on a pair of nodes during the first time period by selectively controlling a respective amount of discharge of an initial charge on each node of the pair of nodes by applying the first and second discharge control signals to respective transistors in a differential transistor pair connected to the pair of nodes, and maintaining the differential voltage on the pair of nodes during a subsequent time period, and generating an amplified differential voltage during at least a portion of the subsequent time period by amplifying the differential voltage.