According to at least one example embodiment, a method and corresponding apparatus for controlling power in a multi-core processor chip include: accumulating, at a controller within the multi-core processor chip, one or more power estimates associated with multiple core processors within the multi-core processor chip. A global power threshold is determined based on a cumulative power estimate, the cumulative power estimate being determined based at least in part on the one or more power estimates accumulated. The controller causes power consumption at each of the core processors to be controlled based on the determined global power threshold. The controller may directly control power consumption at the core processors or may command the core processors to do so.

A single channel receiver includes an input terminal that receives an analog input signal, a mixer that down-mixes the analog input signal by use of a phase- and/or frequency-corrected oscillator frequency signal and shifts complex-valued information contained in the analog input signal to the real part (or alternatively to the imaginary part) to obtain an intermediate real-valued analog signal, an analog-to-digital-converter that converts the intermediate analog signal into an intermediate digital signal, a demodulator that demodulates the intermediate digital signal into a digital output signal, a phase tracking loop that detects zero-crossings in the intermediate digital signal to obtain phase error information representing a phase error in the intermediate digital signal, and an oscillator that generates the phase- and/or frequency-corrected oscillator frequency signal by compensating the phase and/or frequency error in the intermediate digital signal by correcting the phase of the oscillator frequency signal with the phase error information.

The disclosure relates to technology for compensating for I/Q imbalance. An apparatus includes I-path circuitry having a first analog filter configured to filter an I-path signal and Q-path circuitry having a second analog filter configured to filter a Q-path signal. An I/Q imbalance compensation circuit of the apparatus is configured to process digital versions of the I-path signal and the Q-path signal to compensate for mismatch between the I-path circuitry and the Q-path circuitry. A first circuit of the apparatus is configured to apply a coarse adjustment to at least one of the first analog filter or the second analog filter to reduce an initial mismatch between the I-path circuitry and the Q-path circuitry. The first circuit is configured to operate the I/Q imbalance compensation circuit to compensate for a residual mismatch between the I-path circuitry and the Q-path circuitry with the coarse adjustment applied.

An in-phase and quadrature mismatch compensator for a quadrature transmitter includes a delay element, a complex-valued filter and an adder. The delay element receives an input transmit signal and outputs a delayed transmit signal. The complex-valued filter receives the input transmit signal and outputs a selected part of a filtered output transmit signal. The adder adds the delayed transmit signal and the selected part of the filtered output transmit signal and outputs a pre-compensated transmit signal. In one embodiment, the selected part of the filtered output transmit signal includes the real part of the complex-valued output transmit signal. In another embodiment, the selected part of the filtered output transmit signal includes the imaginary part of the complex-valued output transmit signal. Two transmit real-valued compensators are also disclosed that combine the in-phase and quadrature signals before being filtered.

A wireless station includes at least one oscillator to output a reference signal, and an error calculator to calculate a frequency of the reference signal and calculate a frequency error by subtracting a target frequency of the reference signal from the calculated frequency of the reference signal. The wireless station further includes a modulation data generator to generate modulation data by adding a correction value, varying in negative correlation with the frequency error calculated by the error calculator, to data to be transmitted, and a modulator to conduct frequency modulation on the basis of the modulation data and the reference signal.

When the ultra-low power mm-scale sensor node does not have a crystal oscillator and phase-lock loop, it inevitably exhibits significant carrier frequency offset (CFO) and sampling frequency offset (SFO) with respect to the reference frequencies in the gateway. This disclosure enables efficient real-time calculation of accurate SFO and CFO at the gateway, thus the ultra-low power mm-scale sensor node can be realized without a costly and bulky clock reference crystal and also power-hungry phase lock loop. In the proposed system, the crystal-less sensor starts transmission with repetitive RF pulses with a constant interval, followed by the data payload using pulse-position modulation (PPM). A proposed algorithm uses a two-dimensional (2D) fast Fourier transform (FFT) based process that identifies the SFO and CFO at the same time to establish successful wireless communication between the gateway and crystal-less sensor nodes.

A receiving circuit includes: a first receiving terminal for receiving a RF signal; a second receiving terminal for receiving an external oscillating signal generated by an external oscillator; a low-noise amplifier coupled with the first receiving terminal and the second receiving terminal and utilized for generating an output signal; a first switch element positioned between the second receiving terminal and the low-noise amplifier; an in-phase signal processing circuit for generating an in-phase detection signal based on the output signal; an quadrature signal processing circuit for generating an quadrature detection signal based on the output signal; and a calibration circuit for controlling the first switch element and capable of performing an I/Q mismatch calibration operation according to the in-phase detection signal and the quadrature detection signal when the first switch element is turned on.

A modulator operable to control an oscillator is described. The modulator can include a memory that stores oscillator control values and a bit streaming block. The bit streaming block can generate a bit stream based on the oscillator control values and transmit the bit stream to the oscillator to control an oscillation frequency of the oscillator. The modulator can also include a bit streaming loader (BSL). The BSL can receive one or more of the oscillator control values from the memory, generate one or more corresponding bit values based on the one or more of the oscillator control values, and provide the one or more bit values to the bit streaming block. The bit streaming block can then generate the bit stream based the one or more bit values generated by the BSL.

When the ultra-low power mm-scale sensor node does not have a crystal oscillator and phase-lock loop, it inevitably exhibits significant carrier frequency offset (CFO) and sampling frequency offset (SFO) with respect to the reference frequencies in the gateway. This disclosure enables efficient real-time calculation of accurate SFO and CFO at the gateway, thus the ultra-low power mm-scale sensor node can be realized without a costly and bulky clock reference crystal and also power-hungry phase lock loop. In the proposed system, the crystal-less sensor starts transmission with repetitive RF pulses with a constant interval, followed by the data payload using pulse-position modulation (PPM). A proposed algorithm uses a two-dimensional (2D) fast Fourier transform (FFT) based process that identifies the SFO and CFO at the same time to establish successful wireless communication between the gateway and crystal-less sensor nodes.

Certain aspects of the present disclosure relate to methods and apparatus for wireless communication, and more particularly, to methods and apparatus for controlling spurious emissions on devices that support millimeter wave communications. An example method includes providing a local oscillator (LO) signal generated by an LO chain to at least one of a baseband portion or a radio frequency (RF) portion coupled to the baseband portion, detecting interference in the LO signal, and controlling a gain component of the LO chain to adjust an amplitude of the LO signal, based on the detected interference.