A Gaussian frequency shift keying (GFSK) detector for decoding a GFSK signal. The detector includes: a multi-symbol detector and a Viterbi decoder. The multi-symbol detector is configured to: receive a series of samples representing a received GFSK modulated signal; and generate, for each set of samples representing an N-symbol sequence of the GFSK modulated signal, a plurality of soft decision values that indicate the probability that the N-symbol sequence is each possible N-symbol pattern, wherein N is an integer greater than or equal to two. The Viterbi decoder is configured to estimate each N-symbol sequence using a Viterbi decoding algorithm wherein the soft decision values for the N-symbol sequence are used as branch metrics in the Viterbi decoding algorithm.

A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.

Embodiments of the present disclosure provide a signal processing apparatus, a signal transmitting apparatus and a receiver, which are adapted for a frequency division multiplexing system having a high-order modulation format. A receiver having a high-magnification sampling rate by inserting a pilot signal between neighboring subcarriers at a transmitter side, calculating a laser phase noise according to a phase of the pilot signal at a receiver side, and performing down-sampling and equalization processing after performing carrier phase recovery according to the laser phase noise, so that a laser phase noise having a wide frequency may be accurately compensated, thereby having a relatively powerful carrier phase recovery ability.

A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.

A data demodulation method, apparatus, and system are presented. The method includes obtaining notification information indicating that user equipment (UE) is in a high-speed moving state; performing time-frequency synchronization processing on first downlink data according to the notification information to obtain second downlink data; and performing demodulation processing on the second downlink data to obtain third downlink data, where in the demodulation processing, inter-transmission time intervals (TTIs) filtering for a channel estimation is not performed, or a filtering coefficient as a weight of a current TTI for a channel estimation is greater than a filtering coefficient as a weight of a TTI that is at the time when the UE is in the non-high-speed moving state for a channel estimation. The demodulation method is applicable to a high-speed scenario for improving a downlink data throughput of the UE.

A transmitting apparatus includes an OFDM modulator that generates a first modulation symbol by modulating a first information signal using a first modulation scheme, a signal point of the first modulated information signal being arranged at a first position in an in-phase quadrature-phase plane and a second modulation symbol by modulating a second information signal using the first modulation scheme, and by changing a second position at which a signal point of the modulated second information signal is arranged to a third position in the in-phase quadrature-phase plane, wherein the third position is different from the first position. An OFDM modulation signal includes the first modulation symbol and the second modulation symbol, wherein the OFDM modulation signal comprises a plurality of subcarriers. A transmitter transmits the OFDM modulation signal.

A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.

A data demodulation method, apparatus, and system are presented. The method includes obtaining notification information indicating that user equipment (UE) is in a high-speed moving state; performing time-frequency synchronization processing on first downlink data according to the notification information to obtain second downlink data; and performing demodulation processing on the second downlink data to obtain third downlink data, where in the demodulation processing, inter-transmission time intervals (TTIs) filtering for a channel estimation is not performed, or a filtering coefficient as a weight of a current TTI for a channel estimation is greater than a filtering coefficient as a weight of a TTI that is at the time when the UE is in the non-high-speed moving state for a channel estimation. The demodulation method is applicable to a high-speed scenario for improving a downlink data throughput of the UE.

A data demodulation method, apparatus, and system are presented. The method includes obtaining notification information indicating that UE is in a high-speed moving state; performing time-frequency synchronization processing on first downlink data according to the notification information to obtain second downlink data; and performing demodulation processing on the second downlink data to obtain third downlink data, where in the demodulation processing, inter-TTIs filtering for a channel estimation is not performed, or a filtering coefficient as a weight of a current TTI for a channel estimation is greater than a filtering coefficient as a weight of a TTI that is at the time when the UE is in the non-high-speed moving state for a channel estimation. The demodulation method is applicable to a high-speed scenario for improving a downlink data throughput of the UE.

A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.