The present disclosure discloses a method and a device for extracting broadband error calibration parameters, and a computer-readable storage medium. The method includes: performing frequency band splitting on link broadband signals of an ultra-wide band system according to a received frequency band index table to generate sub-bands; extracting an amplitude error and a phase error of each sub-band; and iteratively weighting and accumulating, according to the frequency band index table and a preset broadband weight table, the amplitude error and the phase error of each sub-band one by one to an initial amplitude error compensation parameter and an initial phase error compensation parameter respectively, to synthesize and extract broadband error calibration parameters. The present disclosure can adaptively match a working bandwidth of the current ultra-wide band system, and perform iterative solution on error parameters of a working area in real time, thereby having the advantages of ultra-wide band, high performance, low power consumption and high flexibility.

A modulation format estimation device 100 includes: a frequency shift correction unit 112 configured to estimate the amount of a frequency shift using a baseband signal acquired from a received signal and correct the baseband signal based on an estimation result; a frequency error generation unit 122 configured to generate a plurality of frequency errors from a range set based on an error occurring in the estimation of the frequency shift amount; a frequency error introduction unit 123 configured to acquire learning baseband signals in which each of a plurality of source signals modulated by different modulation formats is frequency-shifted by each frequency error; and a modulation format estimation unit 113 configured to input a corrected baseband signal to a first machine learning model created by machine learning using learning data including the plurality of learning baseband signals and a label, and estimate a modulation format of the received signal.

A direct digital synthesizer (DDS) circuit. The circuit includes a first input to receive a first fixed frequency clock signal having a first frequency, a second input to receive a second fixed frequency clock signal having a second frequency lower than the first frequency, and an output to provide an output frequency that is based at least in part on a frequency control word (FCW). The DDS circuit may include a frequency correction circuit having a first input to receive the first clock signal, a second input to receive the second clock signal, and a third input to receive the FCW, and an output to provide a frequency error of the first clock signal, the frequency error determined using the second clock signal and FCW. Alternatively, or in addition to, the DDS circuit may include an all-digital phase lock loop to correct for frequency wander of the first clock signal.

A carrier frequency tracking method, a signal transmission method, and a related apparatus. The carrier frequency tracking method includes: a terminal device receives a first tracking reference signal from a first transmission reception apparatus of a single frequency network cell; the terminal device receives a second tracking reference signal from a second transmission reception apparatus of the single frequency network cell, where the first tracking reference signal and the second tracking reference signal occupy different time-frequency resources; and the terminal device performs carrier frequency tracking based on at least one of the first tracking reference signal and the second tracking reference signal.

When the ultra-low power mm-scale sensor node does not have a crystal oscillator and phase-lock loop, it inevitably exhibits significant carrier frequency offset (CFO) and sampling frequency offset (SFO) with respect to the reference frequencies in the gateway. This disclosure enables efficient real-time calculation of accurate SFO and CFO at the gateway, thus the ultra-low power mm-scale sensor node can be realized without a costly and bulky clock reference crystal and also power-hungry phase lock loop. In the proposed system, the crystal-less sensor starts transmission with repetitive RF pulses with a constant interval, followed by the data payload using pulse-position modulation (PPM). A proposed algorithm uses a two-dimensional (2D) fast Fourier transform (FFT) based process that identifies the SFO and CFO at the same time to establish successful wireless communication between the gateway and crystal-less sensor nodes.

An apparatus and method for carrier frequency estimation include a carrier frequency estimator having: a frequency input terminal disposed to receive a frequency-domain input signal comprising a plurality of symbols; a plurality of candidate pipelines, each comprising a frequency adder coupled to the frequency input terminal, a bit converter coupled to the frequency adder, a multi-bit buffer coupled to the bit converter; and a correlator coupled to the multi-bit buffer, respectively; and a candidate pipeline selector coupled to the correlators.

The present disclosure relates to a communication method and system for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for Internet of Things (IoT). A method of determining a frequency-domain offset parameter of a preamble in a random access channel and a corresponding user equipment (UE) is provided. The method includes obtaining a random access channel subcarrier spacing Δf.sub.RA, a preamble length L.sub.RA and a uplink (UL) channel subcarrier spacing Δf from a base station and determining a frequency-domain offset parameter k of a preamble in a random access channel based on the obtained random access channel subcarrier spacing Δf.sub.RA, preamble length L.sub.RA and UL channel subcarrier spacing Δf. Other embodiments of the disclosure further provide a random access method, a method for configuring random access information and related device, and a corresponding computer readable medium.

Processing a digital bit stream and systems for implementing the methods are provided. The method includes dividing the digital bit stream into a plurality of data packets. In a first processing block performing a carrier recovery error calculation on a first portion of the plurality of data packets, comprising preforming a first phase locked loop (PLL) function on decimated data of the data packets and performing a carrier recovery operation on the first portion of the plurality of data packets. In a second processing block, in parallel with the processing of the first portion of the plurality of packets, performing the carrier recovery error calculation on a second portion of the plurality of data packets, comprising preforming the first PLL function on decimated data of the data packets and performing the carrier recovery operation on second portion of the plurality of data packets.

A circuit for processing Carrier Aggregation (CA) is provided. The circuit includes a plurality of Component Carrier (CC) processors, each CC processor configured to estimate a frequency offset for a related CC and to compensate the estimated frequency offset, a reference clock generator configured to generate a reference clock using a reference frequency offset as one of frequency offsets output from the plurality of CC processors, a plurality of reception Phase Lock Loop (PLL) units, each reception PLL unit configured to generate a reception carrier frequency for the related CC corresponding to the reference clock, and a plurality of transmission PLL units, each transmission PLL unit configured to generate a transmission carrier frequency for the related CC corresponding to the reference clock.

A receiver detects a received signal, transmitted by a transmitter to carry payload data as Orthogonal Frequency Division Multiplexed (OFDM) symbols in divided frames, each frame including a preamble including plural bootstrap OFDM symbols. A detector circuit detects, from the bootstrap OFDM symbols, a synchronization timing for converting a useful part of the bootstrap OFDM symbols into the frequency domain. A bootstrap processor detects an estimate of the channel transfer function from a first OFDM symbol, and a demodulator circuit recovers the signaling data from the bootstrap OFDM symbols using the estimate. The bootstrap processor includes an up-sampler configured to receive the bootstrap OFDM symbols, to form an up-sampled frequency domain version of the bootstrap OFDM symbol, and an output processor configured to identify a peak correlation result, to determine frequency offset of the received signal from a relative position of the peak correlation result in the frequency domain.