A signal modulation apparatus, a memory storage apparatus, and a signal modulation method are disclosed. The signal modulation apparatus includes an observation circuit, a signal modulation circuit, and a phase control circuit. The signal modulation circuit is configured to generate a second signal according to a first signal and a reference clock signal. A frequency of the first signal is different from a frequency of the second signal. The phase control circuit is configured to obtain an observation information via the observation circuit. The observation information reflects a process variation of at least one electronic component in the signal modulation apparatus. The phase control circuit is further configured to control an offset between the first signal and the reference clock signal according to the observation information.

A reception apparatus includes a detection unit that detects occurrence of a phase slip in phase estimation values of time-series received symbol data, and determines an inclination of the phase slip, a delay processing unit that generates first received signal data obtained by delaying received signal data obtained from the time-series received symbol data by one symbol time interval, a phase shift unit that generates second received signal data by performing phase shift according to the inclination, only in a period in which one symbol time interval elapses, on only the received signal data of a symbol time at which the occurrence of the phase slip is detected among pieces of the received signal data, and a remainder processing unit that derives a remainder of a difference between the second received signal data and the first received signal data.

According to at least one example embodiment, a method and corresponding apparatus for controlling power in a multi-core processor chip include: accumulating, at a controller within the multi-core processor chip, one or more power estimates associated with multiple core processors within the multi-core processor chip. A global power threshold is determined based on a cumulative power estimate, the cumulative power estimate being determined based at least in part on the one or more power estimates accumulated. The controller causes power consumption at each of the core processors to be controlled based on the determined global power threshold. The controller may directly control power consumption at the core processors or may command the core processors to do so.

Multiphase signal generation circuitry receives input signals that are out-of-phase with one another by a quadrature delay (e.g., 90°), and generates output signals that are out-of-phase with one another by half of the quadrature delay. A first input signal may be provided to a first delay circuitry, which is then input to a first phase interpolator. The first delay circuitry is also input to second delay circuitry, which also generates an output that is input to the first phase interpolator. The first phase interpolator outputs a first output signal. The second delay circuitry is input to third delay circuitry, which in turn is input to a second phase interpolator with a second input signal that is out-of-phase with the first input signal by the quadrature delay. The second phase interpolator outputs a second output signal that is out-of-phase with the first output signal by the half of the quadrature delay.

Method of demodulation of M-CPFSK signal, includes receiving the M-CPFSK radio signal; moving it to zero frequency; sampling at no less than double a frequency of symbols; storing the samples with their amplitude and phase for at least L4 symbols; demodulating the sampled signal in three stages, wherein each stage includes iterating over symbol values within a block of symbols, of length is L1, L2 and then L3; in the first stage, N1 symbol sequences out of all possible symbol sequences are iterated over, at the second stage, N2 symbol sequences out of all possible symbol sequences are iterated over, and at the third stage, N3 symbol sequences out of all possible symbol sequences are iterated over, to obtain final symbol values; symbol values obtained at previous stage is used in a next stage to reduce a number of symbol sequences; and determining encoded bits based on final symbol values.

A digital receiver being adapted for receiving an MSK modulated signal, comprises a digital front-end unit (10) adapted for providing samples having a phase value (θ.sub.measure) of a down-mixed signal, a phase compensation unit (11) adapted for compensating the phase value (θ.sub.measure) by delivering a phase offset compensated sample having a phase value (θ.sub.sync), and a coherent demodulator (12) adapted for recovering information content from the phase offset compensated sample. The phase compensation unit (11) is adapted for analyzing a phase value (θ.sub.sync) of the phase offset compensated sample, calculating a phase offset value (θ.sub.offset) based on the phase value (θ.sub.sync) of the phase offset compensated sample, and applying the phase offset value (θ.sub.offset) when delivering a subsequent phase offset compensated sample.

Multiphase signal generation circuitry receives input signals that are out-of-phase with one another by a quadrature delay (e.g., 90°), and generates output signals that are out-of-phase with one another by half of the quadrature delay. A first input signal may be provided to a first delay circuitry, which is then input to a first phase interpolator. The first delay circuitry is also input to second delay circuitry, which also generates an output that is input to the first phase interpolator. The first phase interpolator outputs a first output signal. The second delay circuitry is input to third delay circuitry, which in turn is input to a second phase interpolator with a second input signal that is out-of-phase with the first input signal by the quadrature delay. The second phase interpolator outputs a second output signal that is out-of-phase with the first output signal by the half of the quadrature delay.

When the ultra-low power mm-scale sensor node does not have a crystal oscillator and phase-lock loop, it inevitably exhibits significant carrier frequency offset (CFO) and sampling frequency offset (SFO) with respect to the reference frequencies in the gateway. This disclosure enables efficient real-time calculation of accurate SFO and CFO at the gateway, thus the ultra-low power mm-scale sensor node can be realized without a costly and bulky clock reference crystal and also power-hungry phase lock loop. In the proposed system, the crystal-less sensor starts transmission with repetitive RF pulses with a constant interval, followed by the data payload using pulse-position modulation (PPM). A proposed algorithm uses a two-dimensional (2D) fast Fourier transform (FFT) based process that identifies the SFO and CFO at the same time to establish successful wireless communication between the gateway and crystal-less sensor nodes.

A signal modulation apparatus, a memory storage apparatus, and a signal modulation method are disclosed. The signal modulation apparatus includes an observation circuit, a signal modulation circuit, and a phase control circuit. The signal modulation circuit is configured to generate a second signal according to a first signal and a reference clock signal. A frequency of the first signal is different from a frequency of the second signal. The phase control circuit is configured to obtain an observation information via the observation circuit. The observation information reflects a process variation of at least one electronic component in the signal modulation apparatus. The phase control circuit is further configured to control an offset between the first signal and the reference clock signal according to the observation information.

Methods, systems, and devices for wireless communications are described. A user equipment (UE) may transmit, to a base station, a request for a data transmission that includes multiple subsets of data each associated with a different constellation granularity. In response to the request, the base station may encode the data transmission using multiple different constellation granularities and may transit the encoded data transmission to the UE. For example, the UE may receive the data transmission including a first subset of data that was encoded by the base station using a first constellation granularity and a second subset of data that was encoded by the base station using a second constellation granularity. The UE may then iteratively estimate phase-noises associated with respective subsets of data and perform phase-noise correction operations on the entire data transmission based on the estimated phase-noises.