Embodiments of present disclosure relates to and systems to reduce propagation delays in hardware implementation of 3GPP confidentiality or standardized algorithm 128-EEA3 and 3GPP integrity algorithm 128-EIA3 using ZUC module. The reduction of the propagation delays is achieved by improving or optimizing secondary critical paths, which are subsequent to primary critical path, related to the 3GPP confidentiality or standardized algorithm 128-EEA3 and the 3GPP integrity algorithm 128-EIA3. Non-conventional modifications in the hardware implementation are proposed for the improvement or optimization.

A computing device having a tightly attached or closely attached hardware accelerator directly coupled with one or more processors for efficient uses of the hardware accelerator for executing specific functions are described. According to an embodiment, the hardware accelerator is instantiated inside the main processor unit and interfaces to a load-store unit (LS) using virtual addresses. The hardware accelerator instantiated inside the main processing unit (e.g., core) is referred to as a tightly attached hardware accelerator. In an alternative embodiment, the hardware accelerator is instantiated inside a cluster of processor cores. The hardware accelerator that is instantiated inside the cluster of processor cores but not inside a specific processor core is referred to as a closely attached hardware accelerator.

Hardware circuitry defines logic for both Sbox generation and inverse Sbox generation via generating a multiplicative inverse matrix as a truth table for data. The hardware circuitry receives input plain text to be encrypted. The hardware circuitry divides the input plain text to be encrypted. The hardware circuitry feeds multiplicative inverse values generated from the input plain text to a transformer module for performing affine to encrypt the plain text data. The hardware circuitry receives encrypted data to be decrypted. The hardware circuitry divides the encrypted data to be decrypted. The hardware circuitry feeds multiplicative inverse generated from the encrypted data to the transformer module for performing inverse affine to decrypt the encrypted data.

A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.

Systems and methods for configuring a reduced instruction set computer processor architecture to execute fully homomorphic encryption (FHE) logic gates as a streaming topology. The method includes parsing sequential FHE logic gate code, transforming the FHE logic gate code into a set of code modules that each have in input and an output that is a function of the input and which do not pass control to other functions, creating a node wrapper around each code module, configuring at least one of the primary processing cores to implement the logic element equivalents of each element in a manner which operates in a streaming mode wherein data streams out of corresponding arithmetic logic units into the main memory and other ones of the plurality arithmetic logic units.

A hardware accelerator for accelerating the zero knowledge succinct non-interactive argument of knowledge (zk-SNARK) protocol by reducing the computation time of the cryptographic verification is disclosed. The accelerator includes a zk-SNARK engine having one or more processing units running in parallel. The processing unit can include one or more multiply-accumulate operation (MAC) units, one or more fast Fourier transform (FFT) units; and one or more elliptic curve processor (ECP) units. The one or more ECP units are configured to reduce a bit-length of a scalar d.sub.i in an ECP algorithm used for generating a proof, thereby the cryptographic verification requires less computation power.

A computer processing system have includes a processing unit operably configured to perform a plurality of exponentiation operations and a cryptosystem controller operably configured to load an exponent from the at least one exponentiation operation from a memory to an algorithm controller by first applying a function, wherein the algorithm controller including at least one set of shift registers operably configured to shift a plurality of digits and operably configured to utilize at least one of the plurality of digits as an output.

A method for verification of integrity and decryption of an encrypted message including ordered data blocks, the method performed by a cryptomodule and including storing or activating an integrity key; calculating an initial integrity code; generating a verification key and storing it; for each data block: storing the data block; updating an intermediate integrity code with the integrity key, the data block and the initial integrity code or the intermediate integrity code of the preceding data block; generating an authentication code using the verification key; deleting the data block; analysing the final integrity code; if the integrity is verified: storing or activating a decryption key specific to the encrypted message; for each data block: storing the data block; verifying the authenticity and the row of the data block using its authentication code; decrypting the data block with the decryption key; transmitting to the terminal the decrypted data block.

Methods, systems, and apparatuses associated with hardware mechanisms for link encryption are disclosed. In various embodiments, an interconnect interface is coupled to a processor core to interconnect a peripheral device to the processor core via a link established between the peripheral device and the interconnect interface. The interconnect interface is to select a cryptographic engine of a plurality of cryptographic engines instantiated in the interconnect interface for the link. The cryptographic engine is to symmetrically encrypt data to be transmitted through the link. In more specific embodiments, each of the plurality of cryptographic engines is instantiated for one of a request type on the link, a virtual channel on the link, or a request type within a virtual channel on the link.

Quantum bit decoding apparatus, configured to receive a photon having a qubit encoded in a property of the photon has a demodulation apparatus. The demodulation apparatus includes an optical modulator to randomly apply one of a plurality of modulation values for decoding the qubit to the property of the photon and an optical router to route the photon according to the qubit. The decoding apparatus has an optical delay apparatus having an optical combiner, a first optical path, from the optical router to the optical combiner and a second optical path, from the optical router to the optical combiner. The second path has a different optical path length from the first path. The decoding apparatus has a detection apparatus to detect a photon and to determine whether a detected photon is delayed relative to a reference time and to determine the qubit according to the determined delay.