This application provides a CAN bus circuit and a CAN bus communications method. The CAN bus circuit used for CAN bus communication includes: at least one CAN unit and one bus, where a first CAN unit includes an input port and an output port, the first CAN unit is any one of the at least one CAN unit, the output port is connected to the bus by using a first circuit, the input port is connected to the bus by using a second circuit, a first diode is disposed on the first circuit, and a second diode is disposed on the second circuit.

A transceiver includes a transmitter and a receiver connected to each other by a first line and a second line. The transmitter transmits signals having a first voltage range to the first line and the second line in a first mode, and transmits signals having a second voltage range smaller than the first voltage range to the first line and the second line in a second mode. The transmitter encodes an original payload in the second mode to generate a first payload, and transmits the clock training pattern and the first payload through the first line and the second line.

A signal transmission circuit element, a multiplexer circuit element and a demultiplexer circuit element are disclosed. The signal transmission circuit element is connected among multiple electronic modules so as to transmit an electrical signal. The signal transmission circuit element includes an input terminal, an input equalizer, an output driver and an output terminal. The input terminal is for inputting an electrical signal to the input equalizer. The output driver is electrically connected to the input equalizer. The output terminal is electrically connected to the output driver so as to output the electrical signal. Accordingly, after the input terminal receives the electrical signal, the input equalizer can perform gain compensation on the electrical signal, and then an output capacitance of the electrical signal is driven by the output driver and outputted through the output terminal.

A first physical layer device includes a first transmitter and a first receiver. The first transmitter transmits first data to a second physical layer device over a medium at a first line rate during a first transmit period. The first receiver is configured to not receive data during the first transmit period and an echo reflection period occurring after the first transmit period. The echo reflection period is based on a length of the medium between the first physical layer device and the second physical layer device. The first receiver is configured to, after the echo reflection period, receive second data from the second physical layer device over the medium at a second line rate that is less than the first line rate.

A subscriber station for a serial bus system. The subscriber station encompasses: a communication control device for controlling communication with at least one further subscriber station of the bus system; a transmission/reception device for receiving a message from a bus of the bus system, which message was created by the communication control device or by the at least one further subscriber station of the bus system and is being transferred on the bus; an interference detection unit that is configured to detect interference in the context of transfer of the message on the bus; and an interference processing unit that is configured to evaluate the interference detected by the interference detection unit in terms of the nature and magnitude of the interference, and to adapt communication control by the communication control device to the result of the evaluation of the interference.

The present disclosure relates to a bi-directional bus repeater. The present disclosure further relates to a communication bus including a bi-directional bus repeater, and to a communication system including the communication bus. The bi-directional bus repeater includes a first input terminal, a second input terminal, a first pulldown element connected to the first input terminal, and a second pulldown element connected to the second input terminal. By ensuring that the activation of the first and second pulldown elements is dependent on the state of the corresponding input terminal and the detection of a high-to-low transition of the corresponding other input terminal, the problem of self-locking can be avoided or at least minimized.

A high-speed voltage clamping circuit includes p-type field effect transistor (PFET) biasing circuit, an n-type field effect transistor (NFET) biasing circuit, and a field effect transistor (FET) clamp circuit. The PFET biasing circuit is configured to generate a PFET biasing voltage. The NFET biasing circuit is configured to generate a NFET biasing voltage. The FET clamp circuit is in signal communication with the PFET biasing circuit and the NFET biasing circuit. The PFET biasing circuit controls operation of the clamping circuit in response to a voltage overshoot event and the NFET biasing circuit controls operation of the clamping circuit in response to a voltage undershoot event.

A high-speed voltage clamping circuit includes p-type field effect transistor (PFET) biasing circuit, an n-type field effect transistor (NFET) biasing circuit, and a field effect transistor (FET) clamp circuit. The PFET biasing circuit is configured to generate a PFET biasing voltage. The NFET biasing circuit is configured to generate a NFET biasing voltage. The FET clamp circuit is in signal communication with the PFET biasing circuit and the NFET biasing circuit. The PFET biasing circuit controls operation of the clamping circuit in response to a voltage overshoot event and the NFET biasing circuit controls operation of the clamping circuit in response to a voltage undershoot event.

Devices exchange control signals with each other to ensure proper operation of an overall system. For instance, in a communication system, a baseband processor and a transceiver communicate with each other to exchange information for controlling the respective signal processing parts of the baseband processor and the transceiver. While Serial Peripheral Interfaces (SPIs) can be used, SPI can be extremely slow, and does not provide a protocol for allowing a complex set of control signals to be exchanged between the baseband processor and transceiver. The present disclosure describes a fast control interface which can support various modes of operation in allowing two devices to communicate with each other quickly and effectively.

A method and apparatus are disclosed for enabling an existing wire supplying DC current to an electrical load of a vehicle to serve as a clean line for transmission of a data signal without interference from electrical systems of the vehicle. The method comprises identifying opposite ends of the existing wire, cutting the wire at the opposite ends and inserting a respective inductor in series with the wire at each of the opposite ends, to define an intermediate wire section that extends between the two inductors, and coupling data transmitting and receiving units to the intermediate section of the wire to permit data transfer between the transmitting and receiving units.