A configurable serial link interface circuit includes a first transceiver for coupling to a first serial link. The first transceiver includes a first transmit circuit to selectively drive first transmit data along the first serial link and a first receive circuit. The first receive circuit selectively receives first receive data along the first serial link. The interface includes a second transceiver for coupling to a second serial link. The second transceiver includes a second transmit circuit to selectively drive second transmit data along the second serial link, a second receive circuit to selectively receive second receive data along the second serial link, and control circuitry to control the selectivity of the first transmit circuit, the second transmit circuit, the first receive circuit and the second receive circuit. For a first mode of operation, the control circuitry configures the first and second transceivers to define a dual-duplex architecture. For a second mode of operation, the control circuitry configures the first and second transceivers to define a single-duplex architecture.

A transmission device of the disclosure includes: a generator unit that generates, on the basis of a control signal, a transmission symbol signal that indicates a sequence of transmission symbols; an output control unit that generates an output control signal on the basis of the transmission symbol signal; and a driver unit that generates, on the basis of the output control signal, a first output signal, a second output signal, and a third output signal. The generator unit generates the transmission symbol signal on the basis of the control signal, to allow the first output signal, the second output signal, and the third output signal to exchange signal patterns with one another.

A transmission device of the disclosure includes: a generator unit that generates, on the basis of a control signal, a transmission symbol signal that indicates a sequence of transmission symbols; an output control unit that generates an output control signal on the basis of the transmission symbol signal; and a driver unit that generates, on the basis of the output control signal, a first output signal, a second output signal, and a third output signal. The generator unit generates the transmission symbol signal on the basis of the control signal, to allow the first output signal, the second output signal, and the third output signal to exchange signal patterns with one another.

A system comprises a plurality of nodes connected in a peer-to-peer network via a communication interface. At least one node of the plurality of nodes comprises a transceiver, at least two connectors, at least one termination resistance module coupled to the transceiver, the at least one termination resistance module providing termination resistance within the node, a first detection circuit coupled to a first connector of the at least two connectors, and a second detection circuit coupled to a second connector of the at least two connectors. The first and second detection circuits are configured to detect that the node is coupled to one or more other nodes in the peer-to-peer network, and automatically adjust the termination resistance based on the detecting.

A reception interface circuit includes a termination circuit, a buffer and an interface controller. The termination circuit is configured to change a termination mode in response to a termination control signal. The buffer is configured to change a reception characteristic in response to a buffer control signal. The interface controller is configured to generate the termination control signal and the buffer control signal such that the reception characteristic of the buffer is changed in association with the change in the termination mode. The reception interface circuit may support various communication standards by changing the reception characteristic of the buffer in association with the termination mode. Using the reception interface circuit, communication efficiency of transceiver systems such as a memory system and/or compatibility between a transmitter device and a receiver device may be improved.

Methods and apparatuses relating to measuring propagation delays through USB retimers are described. In one embodiment, a retimer apparatus includes a receiver to receive a data block and a timestamp for the data block from an upstream device, a buffer to store the data block and the timestamp for transmittal, a controller to modify the timestamp to generate a modified timestamp that includes a time from a receipt of a first portion of the data block in the buffer until a transmittal of the first portion of the data block from the buffer, and a transmitter to transmit the data block and the modified timestamp to a downstream device.

An active termination circuit comprising an input node connected to a transmission line, a first transistor, and a second transistor. The transmission line supplies a signal to the input node. The first transistor is diode connected between a high voltage supply and the input node. The first transistor terminates the signal when the signal is at a low logic level. The second transistor is diode connected between the input node and a low voltage supply. The second transistor terminates the signal when the signal is at a high logic level.

A memory system includes a memory controller and a memory module, where the memory controller is arranged for generating at least a first clock signal and an inverted first clock signal, and the memory module is arranged to receive at least the first clock signal and the inverted first clock signal from the memory controller. In addition, the memory module includes a termination module, and the first clock signal is coupled to the inverted first clock signal through the termination module.

A memory system includes a memory controller and a memory module. The memory controller is arranged for selectively generating at least a clock signal and an inverted clock signal. The memory module includes a first termination resistor, a second termination resistor and a switch module, where a first node of the first termination resistor is to receive the clock signal, a second termination resistor, wherein a first node of the second termination resistor is to receive the inverted clock signal, and the switch module is arranged for selectively connecting or disconnecting a second node of the second termination resistor to a second node of the first termination resistor.

A method for performing memory interface calibration in an electronic device, an associated apparatus, and an associated memory controller are provided, where the method includes: controlling a signal on a digital terminal of the memory controller to switch between a plurality of levels, wherein the digital terminal is coupled to a memory of the electronic device; and based on at least one detection result obtained from detecting the signal, calibrating a logical state of the signal to correspond to a level of the plurality of levels. More particularly, the memory controller may include a plurality of command terminals, a plurality of data terminals, and at least one clock terminal, which are used for coupling the memory controller to the memory. For example, the digital terminal may be a command terminal or a data terminal.