Equalization circuitry for a data channel in an integrated circuit device includes an analog equalization stage coupled to the data channel, and a digital signal processing stage downstream of the analog equalization stage. The digital signal processing stage generates control signals to control the analog equalization stage, and includes a digital equalization stage that operates on output of the analog equalization stage. The analog equalization stage may further include an enhanced processing stage for optical signals, which may be selectably coupled to the analog equalization stage. The analog equalization stage may include at least one feed-forward or feedback equalization stage, and a decision stage that outputs decision signals at one of a first plurality of signal levels. The enhanced processing stage operates on the decision signals to output enhanced decision signals at one of a second plurality of signal levels of higher resolution than the first plurality of signal levels.

an orthogonal frequency division multiplexed (OFDM) output signal produced by a device in response to an OFDM input signal is accessed. The OFDM input signal includes OFDM input symbols in the time domain and the OFDM output signal includes OFDM output symbols in the time domain. The OFDM output symbols are time-aligned to the OFDM input symbols and a phase of the OFDM output signal is de-rotated with respect to the OFDM input signal. A complex equalization filter is applied to the OFDM output symbols in the time domain to obtain an estimate of the OFDM input symbols A distortion signal of the OFDM output signal is determined by subtracting the estimate of the OFDM input symbols. An error vector magnitude (EVM) is determined by dividing a root mean square of the distortion, by a root mean square of the OFDM input signal.

A method of equalizing received packet data in a bus topology network, including: receiving, by a receiver of a second node, a first packet from a first node in a bus topology network in which two or more nodes are connected via a bus; setting, by the receiver, an equalizer coefficient of an equalizer using a first training sequence of the first packet and storing the set equalizer coefficient; receiving, by the receiver, a second packet including a second training sequence shorter than the first training sequence from the first node; and equalizing, by the receiver, the second packet using the stored equalizer coefficient.

A gear shifting technique has been developed in which modulation and equalization are shifted to achieve optional performance. In one form, two or more equalizers, each associated with a demodulator and message decoder, determine if the modulation being used can be increased in complexity in order to increase the channel throughput or determine if the modulation method should be reduced in complexity in order to improve the receiver error performance. The quality metrics can based on which equalizer-demodulator-decoder is set to first detect a valid message. Other factors can be considered with this technique such as a packet-error ratio and a signal-to-noise ratio. In a financial trading system, message erasures can be favored over errored messages by limiting the number of bit or symbol corrections permitted per message to less than the maximum possible for the selected decoding schemes.

An integrated circuit for a receiving link device includes a processing device to detect, using an equalizer of the receiving link device, that a receiver (RX) pre-cursor value is outside of a threshold value based on a target RX tap value. The processing device further generates, based on the detecting, a plurality of tap messages having a plurality of up or down commands to one of decrease or increase a corresponding transmitter (TX) pre-cursor value of a transmitting link device. The processing device further causes the plurality of tap messages to be provided to a local transmitter to be transmitted to the transmitting link device. The plurality of tap messages is to cause the transmitting link device to adjust the corresponding TX pre-cursor value.

A continuous time linear equalizer (CTLE) includes a first circuit path having a step response that increases from an first initial value to a steady state value higher than the first initial value. The CTLE also includes a second circuit path in parallel with the first circuit path, the second circuit path having a step response that increases from a second initial value to a peak and subsequently falls to second steady state value that is approximately equal to the second initial value. The CTLE is configured to combine an output of the first circuit path and an output of the second circuit path.

A high-speed signaling system with adaptive transmit pre-emphasis. A transmit circuit has a plurality of output drivers to output a first signal onto a signal path. A receive circuit is coupled to receive the first signal via the signal path and configured to generate an indication of whether the first signal exceeds a threshold level. A first threshold control circuit is coupled to receive the indication from the receive circuit and configured to adjust the threshold level according to whether the first signal exceeds the threshold level. A drive strength control circuit is coupled to receive the indication from the receive circuit and configured to adjust a drive strength of at least one output driver of the plurality of output drivers according to whether the first signal exceeds the threshold level.

Selection of equalization coefficients to configure a communications link between a receiver in a host system and a transmitter in an optical or electrical communication module is performed by a management entity with access to management registers in the receiver and transmitter. Continuous modification of the selected equalization coefficients is enabled on the communications link after the communications link is established to handle varying operating conditions such as temperature and humidity.

An equalizer that has a wide variable gain range and that can implement equalization for a communication medium such as on-board wiring or a cable having various wiring lengths. The equalizer includes a core circuit and a source follower connected to a subsequent stage of the core circuit. The core circuit includes a differential pair including a first transistor and a second transistor, and a zero point generation circuit connected between a second terminal of the first transistor and a second terminal of the second transistor. The source follower includes a third transistor and a fourth transistor, a variable bias current source is connected to the third and fourth transistors, and a load in which a capacitive element and a resistor element are connected in series via a switching element is connected to wiring that connects the third and fourth transistors to an output terminal.

An apparatus, method and computer program is described comprising receiving data at a receiver of a transmission system; using a receiver algorithm to convert data received at the receiver into an estimate of the first coded data, the receiver algorithm having one or more trainable parameters; generating an estimate of first data bits by decoding the estimate of the first coded data, said decoding making use of an error correction code of said encoding of the first data bits; generating a refined estimate of the first coded data by encoding the estimate of the first data bits; generating a loss function based on a function of the refined estimate of the first coded data and the estimate of the first coded data; updating the trainable parameters of the receiver algorithm in order to minimise the loss function; and controlling a repetition of updating the trainable parameters by generating, for each repetition, for the same received data, a further refined estimate of the first coded data, a further loss function and further updated trainable parameters.