A transmitting device for a random-access communication, includes an encoder that acquires an input message having a sequence of bits. The encoder is configured to form a plurality of blocks from the sequence of bits, and determine a plurality of vectors for the plurality of blocks. The transmitting device further includes a mapper circuit that is configured to construct a symbol vector based on the plurality of vectors. The transmitting device further includes an antenna that is configured to transmit the constructed symbol vector over a radio frequency (RF) signal to a receiving device, where the constructed symbol vector represents a symbol modulated in the radio frequency signal.

Aspects of the disclosure provide for methods and systems for Sub-codebook based Trellis Coded Quantization for CSI Feedback. An aspect of the disclosure provides method executed by a receiver. The method includes receiving a signal from a transmitter, via a communication channel between the receiver and the transmitter. The method further includes estimating parameters associated with the channel based on the received signal. The method further includes obtaining phase information from the estimated parameters. The method further includes applying a trellis coded quantization (TCQ) scheme to the obtained phase information by mapping each sub-codebook index of a set of sub-codebook indices to output bits of each trellis branch making the distance between sub-codebooks maximally equal. The method further includes transmitting a channel state information (CSI) measurement feedback to the transmitter, the CSI measurement feedback based on the TCQ scheme and comprising one or more of: a beginning state, input bits to the TCQ scheme, and a sub-codebook index.

Apparatuses, methods, and systems are disclosed for supporting JED model selection and training. One apparatus includes a processor and a transceiver that receives a configuration from a network device, said configuration indicating at least one of: a set of resources for model training, a type of intended model training, and combinations thereof. The processor selects a Joint Channel Equalization and Decoding (“JED”) model from a set of models based on the received configuration. The processor trains the selected JED model using the received configuration.

Apparatus, systems and methods for error detection in transmissions on a multi-wire interface are disclosed. A method for correcting transmission errors in multi-wire transition-encoded interface may include determining whether a symbol error is present in the sequence of symbols based on a value of an error detection code (EDC) in the received plurality of bits, generating one or more permutations of the sequence of symbols, where each permutation includes one symbol that is different from corresponding symbols in the sequence of symbols and different from corresponding symbols in other permutations. A permutation in the one or more permutations may be identified as including a corrected sequence of symbols when it produces a decoded EDC value that matches an expected EDC value. The expected EDC value may correspond to a predefined value for EDCs transmitted over the multi-wire interface to enable detection of up to two symbol errors at the receiver.

A receiver architecture is described for phase noise compensation in the presence of inter-channel interference (ICI) and inter-symbol interference (ISI), particularly for time-frequency packing (TFP) transmissions. The receiver includes a coarse phase noise (PN) estimator, a PN compensation module, an ICI cancellation module, an ISI compensation module, a FEC decoder, and an iterative PN estimator. The iterative PN estimator receives log likelihood ratio (LLR) information from the decoder and provides an iterative PN estimation to the PN compensation module. The decoder also provides LLR to the ISI compensation module, and to at least one other receiver for another subchannel that is immediately adjacent in frequency. The ICI cancellation module receives decoder output from at least one adjacent subchannel, which the ICI cancellation module uses to provide a ICI-cancelled signal.

A technique for assessing the reliability of bits received by a modulation symbol on a channel is provided. A providing circuit provides an input dataset including a plurality of input values. The input values correspond to different transmit hypotheses according to a modulation alphabet used for encoding the bits in the symbol. A computing circuit performs a first computing step and a second computing step. In the first computing step, a first intermediary dataset is computed by combining the input values of the input dataset according to a first combination scheme. In the second computing step, a second intermediary dataset is computed by combining the input values of the input dataset according to a second combination scheme. The second combination scheme is different from the first combination scheme. An assessing circuit assesses the reliability of the bits based on the first intermediary dataset and the second intermediary dataset.

An apparatus and a method. The apparatus includes a channel estimation (CE) module, including a first input for receiving pilot resource element (RE) observations, a second input for receiving data RE observations, a third input for receiving log-likelihood ratios (LLRs), and an output; a detector, including a first input connected to the output of the CE module, a second input for receiving data RE observations, and an output connected to the third input of the CE module; and a decoder, including an input connected to the third input of the CE module, and an output.

Circuits for producing signals representative of mean and variance estimations for quadrature amplitude modulation (QAM) are provided where the circuits comprise: sequentially repeated first circuit modules and sequentially repeated second circuit modules configured for producing updates in the corresponding estimation iterations. In one embodiment, a closest negative integer power of 2 is used as a substitute multiplicand when multiplying together two or more outputs of hyperbolic function generating units where the substituted for output is less than one. Size and complexity of the corresponding multiplier can then be reduced.

A digital communication receiver uses a maximum likelihood sequence estimation stage to recover symbols from digitized sample values of a received signal. A probability density function is calculated and used to improve a soft decision forward error correction calculation. The results of error decoding, which represent error corrected data bits, are further used to improve the probability density function calculation.

A combined error checker and sequence generator which shares a LFSR is disclosed which reduces complexity, cost, and area required for implementation while also improving timing margin. A clock and data recovery system recovers a data signal received over a channel from a remote transceiver. Control logic selects different modes of operation of the system. An error detector compares the two sequence signals and records errors in response to differences between the two sequence signals. A sequence generator generates a sequence signal for use by the error detector as a reference sequence signal or for transmission to a remote transceiver. The system includes one or more switching elements configured to selectively route the generated sequence as feedback into the sequence generator or the received sequence signal into the sequence generator subject to whether the combined error checker and sequence generator is in error checker mode or sequence generator mode.