H04L25/0328

APPARATUS AND METHOD FOR SINGLE ANTENNA INTERFERENCE CANCELLATION (SAIC) ENHANCEMENT

An interference cancellation (IC) processor, a method, a method of manufacturing a semiconductor device, and a method of constructing an integrated circuit are provided. The IC processor includes a plurality of mono interference cancellation (MIC) filter estimation processors; a combined effective channel calculation processor; a combined filter calculation processor; and a combined filter processor, including a first input connected to the output of the combined filter calculation processor, a second input for receiving a signal for setting a length of the combined filter that is connected to a second input of the IC processor, a third input connected to the input of the MIC-BRC processor, and an output for providing a filtered output of a de-rotated GMSK signal that is connected to a second output of the IC processor that provides a filtered output y.sub.i of the de-rotated GMSK signal.

SYSTEMS AND METHODS FOR PHASE NOISE MITIGATION IN OPTICAL SUPERCHANNELS

A receiver architecture is described for phase noise compensation in the presence of inter-channel interference (ICI) and inter-symbol interference (ISI), particularly for time-frequency packing (TFP) transmissions. The receiver includes a coarse phase noise (PN) estimator, a PN compensation module, an ICI cancellation module, an ISI compensation module, a FEC decoder, and an iterative PN estimator. The iterative PN estimator receives log likelihood ratio (LLR) information from the decoder and provides an iterative PN estimation to the PN compensation module. The decoder also provides LLR to the ISI compensation module, and to at least one other receiver for another subchannel that is immediately adjacent in frequency. The ICI cancellation module receives decoder output from at least one adjacent subchannel, which the ICI cancellation module uses to provide a ICI-cancelled signal.

Flexible adjustment of uplink and downlink ratio configuration
09794859 · 2017-10-17 · ·

An apparatus and method for flexible adjustment of the uplink-downlink ratio configuration for each enhanced node B (eNodeB) within a wireless communications network is disclosed herein. In one embodiment, a given eNodeB is configured to determine a current or subsequent uplink-downlink ratio configuration for a pre-determined time period. The determined current or subsequent uplink-downlink ratio configuration is encoded into a special physical downlink control channel (PDCCH), the special PDCCH included in at least one radio frame according to the pre-determined time period. The radio frame including the special PDCCH is transmitted to user equipment served by the given eNodeB.

Mutual WLAN and WAN interference mitigation in unlicensed spectrum

The disclosure provides for interference mitigation for wireless signals in unlicensed spectrum. A wireless device may receive a combined signal including a first radio access technology (RAT) signal and a second RAT signal. The wireless device may generate, using a first RAT receiver in a first processing path, a channel estimate for the first RAT signal based on a previously decoded signal of the first RAT. The wireless device may reduce interference to the second RAT signal caused by the first RAT signal, in a second processing path, using the channel estimate. The wireless device may further decode the second RAT signal. The wireless device may remodulate the decoded signal using a transmitter to generate a remodulated second RAT signal. The remodulated second RAT signal may be canceled from the combined signal. The wireless device may decode a remaining portion of the combined signal including the first RAT signal.

METHOD AND APPARATUS FOR DATA-AIDED ITERATIVE CHANNEL ESTIMATION
20170238317 · 2017-08-17 ·

An apparatus and a method. The apparatus includes a channel estimation (CE) module, including a first input for receiving pilot resource element (RE) observations, a second input for receiving data RE observations, a third input for receiving log-likelihood ratios (LLRs), and an output; a detector, including a first input connected to the output of the CE module, a second input for receiving data RE observations, and an output connected to the third input of the CE module; and a decoder, including an input connected to the third input of the CE module, and an output.

Symbol boundary detection method and processor

A symbol boundary detection method includes: calculating desired signal power according to a receiving signal by a receiver device; calculating interference power according to the receiving signal by the receiver device; calculating a signal-to-interference power ratio according to the desired signal power and the interference power by the receiver device; finding a best signal-to-interference power ratio to determine a reference symbol boundary time by the receiver device; and processing the receiving signal according to the reference symbol boundary time by the receiver device for a subsequent demodulation process performed by a demodulator circuit.

EFFICIENT METHODS AND RECURSIVE/SCALABLE CIRCUIT ARCHITECTURES FOR QAM SYMBOL MEAN AND VARIANCE ESTIMATIONS
20170264478 · 2017-09-14 ·

Circuits for producing signals representative of mean and variance estimations for quadrature amplitude modulation (QAM) are provided where the circuits comprise: sequentially repeated first circuit modules and sequentially repeated second circuit modules configured for producing updates in the corresponding estimation iterations. In one embodiment, a closest negative integer power of 2 is used as a substitute multiplicand when multiplying together two or more outputs of hyperbolic function generating units where the substituted for output is less than one. Size and complexity of the corresponding multiplier can then be reduced.

DEVICES AND METHODS FOR PARALLELIZED RECURSIVE BLOCK DECODING
20210397450 · 2021-12-23 ·

A decoder for determining an estimate of a vector of information symbols carried by a signal received through a transmission channel represented by a channel matrix is provided. The decoder includes a block division unit configured to divide the vector of information symbols into two or more sub-vectors, each sub-vector being associated with a block level; two or more processors configured to determine, in parallel, candidate sub-vectors and to store the candidate sub-vectors in a first stack. Each processor is configured to determine at least a candidate sub-vector by applying a symbol estimation algorithm and to store each candidate sub-vector with a decoding metric and the block level associated with the candidate sub-vector. The decoding metric is lower than or equal to a decoding metric threshold. A processor among the two or more processors is configured to determine at least a candidate vector from candidate sub-vectors stored in the first stack, the candidate vector being associated with a cumulated decoding metric and to update the decoding metric threshold from the cumulated decoding metric.

A Novel Communication System of High Capacity
20220166653 · 2022-05-26 ·

Two inventive contributions are made for improvement of communications systems. A first derives the channel capacity of a Time-Limited (TL) system across a communications channel contaminated by interference and by noise. The potential increase in channel capacity compared to current communications systems is due to the availability of an arbitrarily large number of Degrees of Freedom (DOF) with finite access Time (FAT) in a TL system. A second takes advantage of the theory established in the first objective to design novel systems, referred to as Mask-Matched TL systems with FAT DOF, or MTF systems for short. The disclosure shows several embodiments of MTF systems where it is possible to improve the capacity of current communications systems, without having to modify or alter their Power Spectral Density, merely by taking advantage of their existing but unexploited FAT DOF through the 3 MTF design steps introduced in this disclosure.

OAM multiplexing communication system and inter-mode interference elimination method

A transmitting station includes a plurality of transmitting weight multiplication units multiplying each of the transmission signal sequences by a transmitting weight, to be converted into M.sub.TX signals corresponding to UCAs forming an M-UCA so as to output the converted signals, and M.sub.TX transmitting OAM mode generation units inputting the signals corresponding to the UCAs and performing DFT on the input signals, so as to output to the corresponding UCA; and a receiving station includes M.sub.RX receiving OAM mode demultiplex units inputting signals from each of the UCAs forming the M-UCA and performing IDFT on the input signals, so as to output by each of received signal sequences, and a plurality of receiving weight multiplication units multiplying for each of them by a receiving weight, so as to demultiplex the spatially multiplexed received signal sequences and to output them in which interference between spatially multiplexed OAM modes is suppressed.