H04L25/063

Partial response receiver

A signaling system is described. The signaling system comprises a transmit device, a receive device including a partial response receive circuit, and a signaling path coupling the transmit device and the receive device. The receive device observes an equalized signal from the signaling path, and includes circuitry to use feedback from the most recent previously resolved symbol to sample a currently incoming symbol. The transmit device equalizes transmit data to transmit the equalized signal, by applying weighting based on one or more data values not associated with the most recent previously resolved symbol value.

METHODS AND SYSTEMS FOR FILTER FREQUENCY RESPONSE SHIFT COMPENSATION FOR WLAN TRAFFIC

Systems and techniques are described that are directed to filter frequency response shift compensation, including compensating for shifting in the rejection band of the filter. Compensation for the shifting in the rejection band can include applying a pre-distortion to attenuate edge resource units (RUs), and applying PHY Protocol Data Unit (PPDU) scheduling schemes. For example, a PPDU scheduling scheme reduce bandwidth in the channel, thereby dropping the out of band RUs. Front ends provide feedback to a respective radio, which allows that radio to apply the appropriate pre-distortion. The front ends can include one or more filters enabling frequency domain coexistence between collocated radios operating in the differing Wi-Fi bands, and a coupler that provides the feedback indicating the frequency response shift to a radio. The radio can then apply a digital pre-distortion to compensate for the shifting in the rejection band.

Methods and systems for filter frequency response shift compensation for WLAN traffic

Systems and techniques are described that are directed to filter frequency response shift compensation, including compensating for shifting in the rejection band of the filter. Compensation for the shifting in the rejection band can include applying a pre-distortion to attenuate edge resource units (RUs), and applying PHY Protocol Data Unit (PPDU) scheduling schemes. For example, a PPDU scheduling scheme reduce bandwidth in the channel, thereby dropping the out of band RUs. Front ends provide feedback to a respective radio, which allows that radio to apply the appropriate pre-distortion. The front ends can include one or more filters enabling frequency domain coexistence between collocated radios operating in the differing Wi-Fi bands, and a coupler that provides the feedback indicating the frequency response shift to a radio. The radio can then apply a digital pre-distortion to compensate for the shifting in the rejection band.

PARTIAL RESPONSE RECEIVER

A signaling system is described. The signaling system comprises a transmit device, a receive device including a partial response receive circuit, and a signaling path coupling the transmit device and the receive device. The receive device observes an equalized signal from the signaling path, and includes circuitry to use feedback from the most recent previously resolved symbol to sample a currently incoming symbol. The transmit device equalizes transmit data to transmit the equalized signal, by applying weighting based on one or more data values not associated with the most recent previously resolved symbol value.

LOW LATENCY MULTI-AMPLITUDE MODULATION RECEIVER
20170353337 · 2017-12-07 ·

A multi-amplitude modulation receiver includes a signal coupler block coupled to a mixer array block receiving a first input signal from the signal coupler block and a second input from a LO circuit that provides N overlapping phase signals. Outputs of the N mixer elements are coupled to a baseband filter (BBF) block then to a decision threshold block including decision threshold elements including a signal input and at least one comparator receiving at least one V.sub.TH value. A phase ordering and mapper block selects M out of the N phases. A digital logic and control block is coupled to control a filter gain and corner frequency of the BBF block and control the V.sub.TH value for the decision threshold block which compares a signal received to the V.sub.TH value. Outputs from the decision threshold block are coupled inputs of an M-input decision combiner which provides a single data output.

METHODS AND SYSTEMS FOR FILTER FREQUENCY RESPONSE SHIFT COMPENSATION FOR WLAN TRAFFIC

Systems and techniques are described that are directed to filter frequency response shift compensation, including compensating for shifting in the rejection band of the filter. Compensation for the shifting in the rejection band can include applying a pre-distortion to attenuate edge resource units (RUs), and applying PHY Protocol Data Unit (PPDU) scheduling schemes. For example, a PPDU scheduling scheme reduce bandwidth in the channel, thereby dropping the out of band RUs. Front ends provide feedback to a respective radio, which allows that radio to apply the appropriate pre-distortion. The front ends can include one or more filters enabling frequency domain coexistence between collocated radios operating in the differing Wi-Fi bands, and a coupler that provides the feedback indicating the frequency response shift to a radio. The radio can then apply a digital pre-distortion to compensate for the shifting in the rejection band.

OFFSET DETECTOR CIRCUIT FOR DIFFERENTIAL SIGNAL GENERATOR, RECEIVER, AND METHOD OF COMPENSATING FOR OFFSET OF DIFFERENTIAL SIGNAL GENERATOR

An offset detector circuit includes a digital signal register storing M unit digital signals received in latest M signal periods, M being a natural number, among digital signals generated based on a single-ended PAM-N signal, N being an odd number, a comparator outputting a comparison signal of a pair of signals included in differential signals generated from a differential signal generator based on the single-ended PAM-N signal, a comparison result register storing M unit comparison signals corresponding to the latest M signal periods among the comparison signals, a pattern detector outputting a detection signal when the M unit digital signals match a predetermined signal pattern, and an offset checker checking patterns of the M unit comparison signals in response to the detection signal, and outputting an offset detection signal when the patterns of the M unit comparison signals match a predetermined offset pattern.

Data carrier apparatus, data carrier drive apparatus, data communication system, image forming apparatus and replacement unit for the same
11743078 · 2023-08-29 · ·

A system includes a data carrier drive apparatus and a data carrier apparatus. The data carrier apparatus includes a unit to output transmission data during a first state and adjustment data during a second state, and a current changer configured to change a current value of a current flowing from the data carrier drive apparatus to the data carrier apparatus according to data values of the transmission data and the adjustment data. The data carrier drive apparatus includes a detector to detect a detection value corresponding to the current value of the current, a determiner to determine the data value of the transmission data by comparing the detection value with a threshold value during the first state, and an updater to update the threshold value based on the detection value during the second state.

Internal clock distortion calibration using DC component offset of clock signal

Several embodiments of electrical circuit devices and systems with clock distortion calibration circuitry are disclosed herein. In one embodiment, an electrical circuit device includes an electrical circuit die having clock distortion calibration circuitry to calibrate a clock signal. The clock distortion calibration circuitry is configured to compare a first duty cycle of a first voltage signal of the clock signal to a second duty cycle of a second voltage signal of the clock signal. Based on the comparison, the clock distortion calibration circuitry is configured to adjust a trim value associated with at least one of the first and the second duty cycles of the first and the second voltage signals, respectively, to calibrate at least one of the first and the second duty cycles and account for duty cycle distortion encountered as the clock signal propagates through a clock tree of the electrical circuit device.

Data recovery technique for time interleaved receiver in presence of transmitter pulse width distortion

This disclosure relates to a receiver that includes a clock and data recovery loop and a phase offset loop. The clock and data recovery loop may be controlled by a sum of gradients for a plurality of data interleaves. The phase offset loop may be controlled by an accumulated differential gradient for each of the data interleaves.