A data transmitting and receiving system includes a first device including an encoder configured to encode row data to generate precoding data and a transmitter configured to transmit the precoding data through a transmission channel and a second device including an integrator configured to perform an integral on the precoding data, an integral sampler including a plurality of samplers configured to output sampling data based on an offset value and an output value of the integrator, a decoder configured to decode outputs of some of the samplers to generate decoded data, and a phase detector configured to detect a phase difference between the precoding data and a clock based on the decoded data and an output of another one of the samplers.

A transceiver circuit includes a receiver front end utilizing a ring oscillator, and a transmitter front end utilizing a pass-gate circuit in a first feedback path across a last-stage driver circuit. The transceiver circuit provides low impedance at low frequency and high impedance at high frequency, and desirable peaking behavior.

A system for communicating information between circuits is described. A transmit circuit provides pulse-amplitude-modulation (PAM) signals via a communication channel to a receiver. A circuit in the receiver determines digital values from the received signals using a time-varying threshold voltage, which varies during the bit-time. This approach may compensate for inter-symbol interference (ISI) to increase the voltage and timing margins of the system.

A method and system for providing pulsed power and data from a main control unit to slave units via a first bus. The main control unit has an AC signal generator for providing a plurality of first pulses (P1) on the bus for providing the power to the slave units. Each slave unit is AC-coupled to the bus via a first series capacitor arranged for converting the first pulses (P1) into second pulses (P2). Data communication from the main control unit to the slave units is established by modulating the first pulses (P1), and by demodulating the second pulses (P2). The modulation may be based on Pulse Position Modulation, Pulse Width Modulation, Pulse Count Modulation, Pulse Amplitude modulation. Zero, one or more bits may be communicated per first pulse. Optionally the slave units may communicate to the main control unit via a second bus.

A signal receiver includes a first preliminary receiver circuit suitable for receiving an input signal and generating a first preliminary reception signal based on a first reference voltage, a second preliminary receiver circuit suitable for receiving the input signal and generating a second preliminary reception signal based on a second reference voltage, a reception circuit suitable for selecting one of the first preliminary reception signal and the second preliminary reception signal in response to a voltage level of a reception signal and generating the reception signal using the selected signal, and a reference voltage generation circuit suitable for adjusting a voltage level of the first reference voltage based on a first offset and adjusting a voltage level of the second reference voltage based on a second offset.

A digital-to-analog converter (DAC) and a method for operating the DAC are disclosed. The DAC receives, over a first channel, a control signal that is transmitted in accordance with a binary protocol. The DAC also receives, over a second channel different than the first channel, data that is transmitted in accordance with a multilevel communication protocol that is different than the binary protocol. The DAC determines a plurality of first and second voltages based on the received data and identifies, based on the control signal, a time when data transmission or reception is switched between first and second antennas. In response to identifying, based on the control signal, the time when data transmission or reception is switched, the DAC outputs the determined plurality of first voltages to a first antenna tuning circuit or the determined plurality of second voltages to a second antenna tuning circuit.

A signal transmitter circuit includes an output driver circuit configured to transmit a signal using a multi-level pulse amplitude modulation (PAM) scheme comprising a plurality of discreet signal levels. During operation, the output driver initiates a first transition of the signal to a first level of the multi-level PAM scheme from a second level of the multi-level PAM scheme, and initiates a second transition of the signal to the first level from a third level of the multi-level PAM scheme. The signal transmitter further includes a control circuit configured to control a slew rate of the signal transmitter circuit to cause the signal to reach a threshold voltage level at a first time, the first time occurring a first duration of time after the first transition is initiated, and to cause the signal to reach the threshold voltage level at a second time, the second time occurring the first duration of time after the second transition is initiated.

For some applications such as high-speed communication over short-reach links, the complexity and associated high latency provided by existing modulators may be unsuitable. According to an aspect, the present disclosure provides a modulator that can reduce latency for applications such as 40G/100G communication over copper cables or SMF. The modulator has a symbol mapper for mapping a bit stream into symbols, and a multi-level encoder including an inner encoder and an outer encoder for encoding only a portion of the bit stream. In some implementations, the multi-level encoder is configured such that an information block size of the inner encoder is small and matches a field size of the outer encoder. Therefore, components that would be used to accommodate larger block sizes can be omitted. The effect is that complexity and latency can be reduced. According to another aspect, the present disclosure provides a demodulator that is complementary to the modulator.

Provided is a digital transmitting module included in a host device connectable to a client device. A digital transmitting module included in a host device connectable to a client device, the digital transmitting module may include: a clock generator which provides the host device with a clock whose one cycle is comprised of T1, T2, T3 and T4 connected sequentially, and a voltage encoder which receives the clock from the clock generator, receives a digital bit from the host device, generates a voltage pulse by encoding the digital bit based on the clock, and then transmits the voltage pulse to the client device.

A transceiver circuit includes a receiver front end utilizing a ring oscillator, and a transmitter front end utilizing a pass-gate circuit in a first feedback path across a last-stage driver circuit. The transceiver circuit provides low impedance at low frequency and high impedance at high frequency, and desirable peaking behavior.