A system and method for DC balanced transition encoding. In some embodiments, the method includes: generating a set of candidate encoding keys for a set of raw data words; selecting a first encoding key, of the set of candidate encoding keys, based on a first disparity contribution; and encoding the raw data words with the first encoding key, the first disparity contribution being a difference between the number of ones and the number of zeros in the result of encoding the set of raw data words with the first encoding key.

A system and method for DC balanced transition encoding. In some embodiments, the method includes: generating a set of candidate encoding keys for a set of raw data words; selecting a first encoding key, of the set of candidate encoding keys, based on a first disparity contribution; and encoding the raw data words with the first encoding key, the first disparity contribution being a difference between the number of ones and the number of zeros in the result of encoding the set of raw data words with the first encoding key.

A device for manipulating interface signals includes a slave interface, which is connectable to a master interface of a control device, a master interface, which is connectable to a slave interface of a measuring device, and a circuit configuration, which is supplied with at least one data-input signal per interface, and which outputs a corresponding data-output signal per data-input signal to the respective other interface. The circuit configuration includes at least one manipulation unit, to which a data-input signal and a substitute-data signal are supplied and which outputs a corresponding data-output signal, as well as a protocol unit, to which at least one protocol-relevant interface signal is supplied and which, based on manipulation rules and information received with the at least one protocol-relevant interface signal, chooses when the at least one manipulation unit outputs the corresponding data-input signal or the substitute-data signal as data-output signal.

A device for manipulating interface signals includes a slave interface, which is connectable to a master interface of a control device, a master interface, which is connectable to a slave interface of a measuring device, and a circuit configuration, which is supplied with at least one data-input signal per interface, and which outputs a corresponding data-output signal per data-input signal to the respective other interface. The circuit configuration includes at least one manipulation unit, to which a data-input signal and a substitute-data signal are supplied and which outputs a corresponding data-output signal, as well as a protocol unit, to which at least one protocol-relevant interface signal is supplied and which, based on manipulation rules and information received with the at least one protocol-relevant interface signal, chooses when the at least one manipulation unit outputs the corresponding data-input signal or the substitute-data signal as data-output signal.

A system that includes a Viterbi Equalizer having adaptive signal levels is disclosed. Each branch metric of the Viterbi Equalizer compares the value of the incoming bit to one of a plurality of different expected signal levels. A set of default signal values may be used by the Viterbi Equalizer. The system is also configured to determine whether these default expected signal levels are acceptable by monitoring the incoming data bits. If it is determined that the actual signal levels of the incoming data bits differ from the default expected signal levels by more than a predetermined amount, the signal levels used by the Viterbi Equalizer may be changed from default signal levels to the adaptive signal levels. The adaptive signal levels may be determined using the synchronization pattern.

A system that includes a Viterbi Equalizer having adaptive signal levels is disclosed. Each branch metric of the Viterbi Equalizer compares the value of the incoming bit to one of a plurality of different expected signal levels. A set of default signal values may be used by the Viterbi Equalizer. The system is also configured to determine whether these default expected signal levels are acceptable by monitoring the incoming data bits. If it is determined that the actual signal levels of the incoming data bits differ from the default expected signal levels by more than a predetermined amount, the signal levels used by the Viterbi Equalizer may be changed from default signal levels to the adaptive signal levels. The adaptive signal levels may be determined using the synchronization pattern.

A method for testing on-die capacitors is provided. The method comprises transmitting, during a first time period, a first modulated testing signal from a first transmitter port of a transmitter to a first receiver port of a receiver along a first path of a differential signal, the first receiver port connected to a first on-die capacitor in the receiver along the first path; driving, during the first time period, a constant voltage on a second transmitter port of the transmitter to a second receiver port of the receiver along a second path of the differential signal comprising a second on-die capacitor; and determining whether the first on-die capacitor is functional, based on the first modulated testing signal.

A method for testing on-die capacitors is provided. The method comprises transmitting, during a first time period, a first modulated testing signal from a first transmitter port of a transmitter to a first receiver port of a receiver along a first path of a differential signal, the first receiver port connected to a first on-die capacitor in the receiver along the first path; driving, during the first time period, a constant voltage on a second transmitter port of the transmitter to a second receiver port of the receiver along a second path of the differential signal comprising a second on-die capacitor; and determining whether the first on-die capacitor is functional, based on the first modulated testing signal.

According to one embodiment, according to one embodiment, an IC card executing a command from a processing apparatus includes a communication unit and a processing unit. The communication unit transmits/receives data to/from the processing apparatus. Upon receiving, through the communication unit, a first command requesting transmission of data in a first frame not including a start code or an end code, the processing unit transmits data in the first frame through the communication unit.

According to one embodiment, according to one embodiment, an IC card executing a command from a processing apparatus includes a communication unit and a processing unit. The communication unit transmits/receives data to/from the processing apparatus. Upon receiving, through the communication unit, a first command requesting transmission of data in a first frame not including a start code or an end code, the processing unit transmits data in the first frame through the communication unit.