Physical layer devices and related methods for determining Bit Error Rates (BERs) and correcting errors in signals received through shared transmission media of wireless local area networks are disclosed. A physical layer device is configured to identify coding violations in received signal, determine a rate of the coding violations in the signal, and estimate a BER of the signal to be equal to the determined rate of the coding violations. A physical layer device is configured to invert a half symbol immediately preceding or immediately following a coding violation based, at least in part, on signal integrities of the half symbol immediately preceding and the half symbol immediately following the coding violation to correct a bit error.

This application relates to methods and apparatus for transfer of multiple digital data streams, especially of digital audio data over a single communications link such as a single wire. The application describes audio interface circuitry comprising a pulse-length-modulation (PLM) modulator. The PLM is responsive to a plurality of data streams (PDM-R, PDM-L), to generate a series of data pulses (PLM) with a single data pulse having a rising and falling edge in each of a plurality of transfer periods defined by a first clock signal (TCLK). The timing of the rising and falling edge of each data pulse is dependent upon a combination of the then current data samples from the plurality of data streams. The duration and position of the data pulse in the transfer window in effect defines a data symbol encoding the data. Circuitry for receiving and extracting the data is also disclosed. An interface receives the stream of data pulses (PLM) and data extraction circuitry samples the data pulse to determine which of the possible data symbols the pulse represents and determines a data value for at least one received data stream.

A power transmitter includes: a first switch coupled between a first node and a reference voltage node; a second switch configured to be coupled between a power supply and the first node; a coil and a capacitor coupled in series between the first node and the reference voltage node; a first sample-and-hold (S&H) circuit having an input coupled to the first node; and a timing control circuit configured to generate a first control signal, a second control signal, and a third control signal that have a same frequency, where the first control signal is configured to turn ON and OFF the first switch alternately, the second control signal is configured to turn ON and OFF the second switch alternately, and where the third control signal determines a sampling time of the first S&H circuit and has a first pre-determined delay from a first edge of the first control signal.

A communication system has a galvanic isolation link coupling a first circuit to a second circuit. The first circuit transmits first data signals to the second circuit and receives second data signals from the second circuit in response to the first data signals. The data signals are transmitted in consecutive time slots of a determined time duration via the galvanic isolation link. The first data signals include polling signals transmitted from the first circuit to the second circuit during consecutive time slots, and on-demand access requests transmitted from the first circuit to the second circuit. The second data signals include status response signals transmitted from the second circuit to the first circuit in response to polling signals received from the first circuit, and access response signals transmitted from the second circuit to the first circuit in response to access requests received from the first circuit.

A power transmitter includes: a first switch coupled between a first node and a reference voltage node; a second switch configured to be coupled between a power supply and the first node; a coil and a capacitor coupled in series between the first node and the reference voltage node; a first sample-and-hold (S&H) circuit having an input coupled to the first node; and a timing control circuit configured to generate a first control signal, a second control signal, and a third control signal that have a same frequency, where the first control signal is configured to turn ON and OFF the first switch alternately, the second control signal is configured to turn ON and OFF the second switch alternately, and where the third control signal determines a sampling time of the first S&H circuit and has a first pre-determined delay from a first edge of the first control signal.

Waveform-coding is applied to map successive on-off-keying (OOK) data bits onto successive multicarrier modulated symbols in time domain, wherein each multicarrier modulated symbol includes a set of sub-carriers in which alternating sub-carriers are set to non-zeros and zeros in frequency domain. The waveform coded multicarrier modulated symbols are up-converted to a carrier frequency to provide a data signal that is transmitted over a wireless channel.

A system and method for recovering encoded data from a modulated baseband signal is disclosed. Aspects and embodiments of the system and method include receiving an analog input signal representing a modulated baseband signal, counting clock cycles of a reference clock, detecting a first transition and a second transition of the analog input signal indicating a first change and a second change in the modulated baseband signal, storing a first counter value corresponding to an amount of clock cycles elapsed between the first transition and the second transition, and determining a binary-valued bit sequence corresponding to the first counter value.

A 10BASE-T1S PHY method and apparatus are provided for receiving an analog MDI signal conveying DME-encoded data at a receiver comparator to generate a digital output signal, processing the digital output signal using a pulse encoder to generate a pulse-coded output signal with pulses generated at each rising or falling transition in the digital output signal, processing the pulse-coded output signal with an output driver to generate a pulse-coded driver output signal that is transmitted to a receiver interface pin RX, processing the pulse-coded driver output signal with an input comparator to generate a pulse-coded comparator output signal, processing the pulse-coded comparator output signal using a pulse decoder to generate a DME-encoded PMA input signal in which timing asymmetries caused by processing at the receiver comparator and/or output driver have been eliminated, and then processing DME-encoded PMA input signal at a digital PHY circuit in the Ethernet PHY.

A control panel for a fire alarm system includes a microprocessor operable to send and receive data. The microprocessor has a serial peripheral interface with a master port and a slave port. A computing device has a Differential Manchester encoder configured to encode data received from the master port and a Differential Manchester decoder configured to decode frames and send the decoded data to the slave port. A method of sending and receiving data is also disclosed.

A method of transmitting a Physical Layer Convergence Procedure (PLCP) frame in a Very High Throughput (VHT) Wireless Local Area Network (WLAN) system includes generating a MAC Protocol Data Unit (MPDU) to be transmitted to a destination station (STA), generating a PLCP Protocol Data Unit (PPDU) by adding a PLCP header, including an L-SIG field containing control information for a legacy STA and a VHT-SIG field containing control information for a VHT STA, to the MPDU, and transmitting the PPDU to the destination STA. A constellation applied to some of Orthogonal Frequency Division Multiplex (OFDM) symbols of the VHT-SIG field is obtained by rotating a constellation applied to an OFDM symbol of the L-SIG field.