A method of encoding input data includes dividing the input data into a plurality of data packets, an input packet of the plurality of data packets including a plurality of digits in a first base system, base-converting the input packet from the first base system to generate a base-converted packet including a plurality of converted digits in a second base system, the second base system having a base value lower than that of the first base system, and incrementing the converted digits to generate a coded packet for transmission through a communication channel.

A 10BASE-T1S PHY method and apparatus are provided for receiving an analog MDI signal conveying DME-encoded data at a receiver comparator to generate a digital output signal, processing the digital output signal using a pulse encoder to generate a pulse-coded output signal with pulses generated at each rising or falling transition in the digital output signal, processing the pulse-coded output signal with an output driver to generate a pulse-coded driver output signal that is transmitted to a receiver interface pin RX, processing the pulse-coded driver output signal with an input comparator to generate a pulse-coded comparator output signal, processing the pulse-coded comparator output signal using a pulse decoder to generate a DME-encoded PMA input signal in which timing asymmetries caused by processing at the receiver comparator and/or output driver have been eliminated, and then processing DME-encoded PMA input signal at a digital PHY circuit in the Ethernet PHY.

Transmitter circuitry includes inversion circuitry, first transform circuitry, and selection circuitry. The inversion circuitry generates a first transformed data word by inverting one or more of a plurality of bits of a first data word. The first transform circuitry generates a second transformed data word by performing a first invertible operation on the first data word and a second data word. The selection circuitry selects one of the first data word, the first transformed data word, and the second transformed data word based on a first number of bit inversions between the first data word and the second data word, a second number of bit inversions between the first transformed data word and the second data word, and a third number of bit inversions between the second transformed data word and the second data word. The selection circuitry further outputs the selected data word.

A method of encoding input data includes dividing the input data into a plurality of data packets, an input packet of the plurality of data packets including a plurality of digits in a first base system, base-converting the input packet from the first base system to generate a base-converted packet including a plurality of converted digits in a second base system, the second base system having a base value lower than that of the first base system, and incrementing the converted digits to generate a coded packet for transmission through a communication channel.

A signal processing method of a semiconductor device, the method including: receiving a first digital code of a first digital signal; generating a constraint vector; masking the first digital code with a transmitting mask based on the constraint vector; and outputting the masked first digital code and a Data Bus Inversion (DBI) bit of the mask.

The present disclosure relates to a data transmission method, device, system, and display device. The method includes encoding clock training data to obtain two sets of encoded data corresponding to the clock training data and complementary to each other, sending a specified set of encoded data in the two sets of encoded data to a receiving end when positive and negative pins of the transmitting end and the receiving end are correspondingly connected, sending other set of coded data in the two sets of coded data than the specified set of encoded data to the receiving end when the positive and negative pins of the transmitting end and the receiving end are reversely connected. The receiving end may be configured to perform clock training according to the received encoded data.

The invention relates to a method for the secured digital transmission of current measurement values and to a battery (1) and a battery controller (10) which are suitable for carrying out the method. The method has the steps of detecting (S1, S2) an amplitude of a battery current (I.sub.B) in a battery (1) using a first and a second sensor (2, 3), generating (S3, S4) a first and a second bit sequence, each of which describes the detected amplitude, generating a mirrored second bit sequence (21) by reversing (S5) a sequence of the bits provided by the second bit sequence (20), simultaneously transmitting (S6) the first bit sequence via a first data bus (5) and the mirrored second bit sequence (21) via a second data bus (6) to a battery controller (10), generating a second bit sequence (20) by reversing (S7) a sequence of the bits provided by the mirrored second bit sequence (21) after the simultaneous transmission (S6), and finally detecting (S8) a possible error in the first bit sequence or the second bit sequence (20) by comparing the first bit sequence (20) with the second bit sequence (21). Transmission faults are thus detected in particular in a transmission path between the sensors of the battery and the battery controller, said faults being caused by a common disturbance. Additionally, faults can also be detected which are caused by a disturbance that only affects one of the sensors or a part of the transmission path.

A light speed camera system, with a camera module, which has a light speed photo sensor, preferably based on mixed photo detection, having at least one reception pixel, and with an illumination module which has an illumination light source, wherein the illumination module and the camera module each have a transmission circuit which is formed in such a way that a first signal as a differential signal and a second signal as a modulated basic voltage can be transmitted between the camera module and illumination module via a differential signal line is provided.

A system and method for line coding of data. A serial transmitter includes a forward error correction encoding circuit followed by a bit conditioning circuit. The bit conditioning circuit counts the lengths of runs of consecutive identical digits and, when the count reaches a threshold, flips a bit. A serial receiver receives the data from the serial transmitter. The serial receiver includes a forward error correction decoding circuit, which re-flips bits flipped by the bit conditioning circuit of the serial transmitter.

There is disclosed integrated circuitry having a bit receiving arrangement adapted for receiving, in parallel, a plurality of data bits, the bit receiving arrangement further being adapted for receiving a data bit inversion bit associated to the plurality of data bits, the data bit inversion bit being for indicating whether the bits of the plurality of data bits are inverted. The integrated circuitry also has a bit inversion arrangement adapted for inverting the bits of the plurality of data bits based on a comparison between the received data bit inversion bit and an inversion estimate bit, the inversion estimate bit being determined based on the plurality of data bits. The disclosure also pertains to related methods and devices.