A radar hardware accelerator (HWA) includes a fast Fourier transform (FFT) engine including a pre-processing block for providing interference mitigation and/or multiplying a radar data sample stream received from ADC buffers within a split accelerator local memory that also includes output buffers by a pre-programmed complex scalar or a specified sample from an internal look-up table (LUT) to generate pre-processed samples. A windowing plus FFT block (windowed FFT block) is for multiply the pre-processed samples by a window vector and then processing by an FFT block for performing a FFT to generate Fourier transformed samples. A post-processing block is for computing a magnitude of the Fourier transformed samples and performing a data compression operation for generating post-processed radar data. The pre-processing block, windowed FFT block and post-processing block are connected in one streaming series data path.

A method is provided. In some examples, the method includes generating, by processing circuitry, a spread of chips representing an input bit. In addition, the method includes converting, by the processing circuitry, the spread of chips to a plurality of symbols comprising a pair of symbols. The method also includes mapping, by the processing circuitry, the pair of symbols to a single carrier signal and generating, by the processing circuitry, a radio-frequency (RF) signal based on the single carrier signal. The method further includes transmitting, by the processing circuitry via an antenna, the RF signal.

Various embodiments of this disclosure relate to generation and reception of signals comprising cyclically shifted basis functions. A device may obtain a set of modulation symbols and modulate a plurality of basis functions based on the set of modulation symbols to generate a signal. The plurality of basis functions may comprise cyclically shifted versions of a basis function and a periodic autocorrelation function of the basis function may comprise an ideal (e.g., perfect) periodic autocorrelation function.

In an embodiment, an electronic device may include a first frequency synthesizing circuit outputting a second electronic signal from a first electronic signal, a second frequency synthesizing circuit outputting a fourth electronic signal for converting a frequency of a third electronic signal obtained from the first electronic signal based on the second electronic signal, and a communication processor. The communication processor may be configured to transmit, to the first frequency synthesizing circuit, a first parameter indicating a frequency of the second electronic signal, and changing based on a first preset frequency interval according to a first preset period. The communication processor may be configured to transmit, to the second frequency synthesizing circuit, a second parameter indicating a frequency of the fourth electronic signal based on a frequency of a second clock signal, and changing based on a second preset frequency interval different from the first preset frequency interval.

A radar hardware accelerator (HWA) includes a fast Fourier transform (FFT) engine including a pre-processing block for providing interference mitigation and/or multiplying a radar data sample stream received from ADC buffers within a split accelerator local memory that also includes output buffers by a pre-programmed complex scalar or a specified sample from an internal look-up table (LUT) to generate pre-processed samples. A windowing plus FFT block (windowed FFT block) is for multiply the pre-processed samples by a window vector and then processing by an FFT block for performing a FFT to generate Fourier transformed samples. A post-processing block is for computing a magnitude of the Fourier transformed samples and performing a data compression operation for generating post-processed radar data. The pre-processing block, windowed FFT block and post-processing block are connected in one streaming series data path.

A receiver is configured to detect a plurality of signals on a plurality of subbands over a communication channel that operates on a shared or an unlicensed spectrum. Additionally, the receiver is configured to perform joint correlation over a time domain and a frequency domain of each successive signal of the plurality of signals. Moreover, the receiver is configured to determine a sequence based on the joint correlation. Additionally, the receiver is configured to decode transmission information from the sequence.

A wireless communication system, comprising one or several nodes (A) equipped by a wireless radio interface that is adapted for transmitting digital messages modulated in the form of a series of frequency chirps, for example, LoRa-modulated radio signals. The message is received simultaneously by several base stations (C, D, E), and a server (S) is arranged for dividing the frames by the diverse stations and recombining a corrected frame for the intended recipient (B) based on error codes. Advantageously, the base stations being adapt their timing error compensation strategy when the error codes indicate a corruption of the message.

A method and apparatus for underwater acoustic communication are disclosed. A data packet frame structure in the communication transmission includes a preamble, a synchronization code, and a data code. A guard interval is disposed between the preamble and the synchronization code. This method utilizes the different impact response environments of linear frequency modulation signals in different frequency bands to obtain the mapping relationships corresponding to the characteristics of the impulse responses in the frequency band, and adopts the quadrature phase shift keying (QPSK) modulation method to convert four groups of LMF signals with different center frequencies and the same modulation frequency, representing different symbols for signal transmission, where the LFM carrier signal of each center frequency can represent two bits of binary information to improve transmission efficiency. The apparatus for underwater acoustic communication also has the above-mentioned technical effects.

A gateway device having a baseband processor for processing a plurality signals carrying a digital information modulated in the form of chirp signal, the chirp signals being either base chirps, for which the frequency changes from an initial instant to a final instant according to a predetermined base chirp function or modulated chirps, whose instantaneous frequencies vary according to one of a plurality of a functions that differ from said base chirp function, characterized in that the gateway device is arranged for simultaneously demodulating a plurality of signals having received at a same frequency and exhibiting different bitrates.

Advanced modulation and demodulation schemes for LoRa or equivalent chirp spread spectrum transmissions, with differential modulation and symbol repetition improve the sensitivity in combination with soft demodulation methods.