A synchronizer can include a symbol estimator, an inner-pattern de-mapper, a timing tracker, and a correlator. The symbol estimator can be configured to estimate one or more symbols of a received signal based on a phase signal. The inner-pattern de-mapper can be configured to de-map the one or more symbols to generate an inner-pattern de-mapped symbol estimation. The timing tracker can be configured to accumulate the inner-pattern de-mapped symbol estimation and to determine a peak position based on the accumulated inner-pattern de-mapped symbol estimation. The correlator can be configured to correlate the accumulated inner-pattern de-mapped symbol estimation based on a reference signal. The correlation of the accumulated inner-pattern de-mapped symbol estimation can be independent of a signal over sampling rate (OSR). The synchronizer can be adapted in a long range Bluetooth low energy (BLE) receiver.

Apparatuses and methods related to digital mobile radio (DMR) with enhanced transceiver are disclosed herein. The transceiver detects waveforms of signals received by a digital mobile station radio (MS). By detecting whether the waveforms of the signals, the transceiver allows a digital baseband processor of the MS to remain in a sleep state while the signals are being detected by the DMR, thereby reducing an amount of power used while the signals are being detected.

Methods, systems and device for achieving synchronization in an orthogonal time frequency space (OTFS) signal receiver are described. An exemplary signal reception technique includes receiving an OTFS modulated wireless signal comprising pilot signal transmissions interspersed with data transmissions, calculating autocorrelation of the wireless signal using the wireless signal and a delayed version of the wireless signal that is delayed by a pre-determined delay, thereby generating an autocorrelation output, processing the autocorrelation filter through a moving average filter to produce a fine timing signal. Another exemplary signal reception technique includes receiving an OTFS modulated wireless signal comprising pilot signal transmissions interspersed with data transmissions, performing an initial automatic gain correction of the received OTFS wireless signal by peak detection and using clipping information, performing coarse automatic gain correction on results of a received and initial automatic gain control (AGC)-corrected signal.

A receiver detects a received signal, transmitted by a transmitter to carry payload data as Orthogonal Frequency Division Multiplexed (OFDM) symbols in divided frames, each frame including a preamble including plural bootstrap OFDM symbols. A detector circuit detects, from the bootstrap OFDM symbols, a synchronization timing for converting a useful part of the bootstrap OFDM symbols into the frequency domain. A bootstrap processor detects an estimate of the channel transfer function from a first OFDM symbol, and a demodulator circuit recovers the signaling data from the bootstrap OFDM symbols using the estimate. The bootstrap processor includes an up-sampler configured to receive the bootstrap OFDM symbols, to form an up-sampled frequency domain version of the bootstrap OFDM symbol, and an output processor configured to identify a peak correlation result, to determine frequency offset of the received signal from a relative position of the peak correlation result in the frequency domain.

The communication process for high-sensitivity and synchronous demodulation signals between a transmitter (2) and a receiver (3) comprises a first synchronisation phase followed by a modulation and demodulation phase of the data. To achieve this, the transmitter transmits a pseudo-periodic chirp signal to the receiver, where a frequency conversion of the chirp signal is performed in a mixer (33) by an oscillating signal (So) at constant frequency of a local oscillator (34) to supply an intermediate signal, which is filtered and sampled for a logic unit (37). An assembly (38) of m pairs DFT blocks phase-shifted in relation to one another and operating in parallel is provided in the logic unit. A processing unit (39) receives the result of the pairs of the assembly to determine frequency and phase errors between the transmitter and the receiver on the basis of two peaks detected by one of the pairs above a threshold to synchronise the receiver.

Methods, systems and device for achieving synchronization in an orthogonal time frequency space (OTFS) signal receiver are described. An exemplary signal reception technique includes receiving an OTFS modulated wireless signal comprising pilot signal transmissions interspersed with data transmissions, calculating autocorrelation of the wireless signal using the wireless signal and a delayed version of the wireless signal that is delayed by a pre-determined delay, thereby generating an autocorrelation output, processing the autocorrelation filter through a moving average filter to produce a fine timing signal. Another exemplary signal reception technique includes receiving an OTFS modulated wireless signal comprising pilot signal transmissions interspersed with data transmissions, performing an initial automatic gain correction of the received OTFS wireless signal by peak detection and using clipping information, performing coarse automatic gain correction on results of a received and initial automatic gain control (AGC)-corrected signal.

Methods, systems and device for achieving synchronization in an orthogonal time frequency space (OTFS) signal receiver are described. An exemplary signal reception technique includes receiving an OTFS modulated wireless signal comprising pilot signal transmissions interspersed with data transmissions, calculating autocorrelation of the wireless signal using the wireless signal and a delayed version of the wireless signal that is delayed by a pre-determined delay, thereby generating an autocorrelation output, processing the autocorrelation filter through a moving average filter to produce a fine timing signal. Another exemplary signal reception technique includes receiving an OTFS modulated wireless signal comprising pilot signal transmissions interspersed with data transmissions, performing an initial automatic gain correction of the received OTFS wireless signal by peak detection and using clipping information, performing coarse automatic gain correction on results of a received and initial automatic gain control (AGC)-corrected signal.

Apparatuses and methods related to digital mobile radio (DMR) with enhanced transceiver are disclosed herein. The transceiver detects waveforms of signals received by a digital mobile station radio (MS). By detecting whether the waveforms of the signals, the transceiver allows a digital baseband processor of the MS to remain in a sleep state while the signals are being detected by the DMR, thereby reducing an amount of power used while the signals are being detected.

A receiver-implemented method is for measuring a periodically modulated signal. The method includes applying a received periodically modulated signal to a mixer of a receiver, the periodically modulated signal not synchronized with the receiver, and tuning a local oscillator (LO) of the mixer using an estimate of actual carrier frequency and an estimate of an arbitrary waveform generator (AWG) sampling rate to obtain a digitized intermediate frequency (IF) signal. The method further includes applying a short time Fourier transform (STFT) to the digitized IF signal, extracting a carrier frequency offset and a AWG sampling rate offset based on the applied STFT, compensating for the carrier frequency offset, and applying a digital correction to the STFT to compensate for the AWG sampling rate offset. Compensating for the carrier frequency offset may include retuning the LO to obtain a new digitized IF signal to which the digital correction is applied.

A method for improving timing between solid state devices, e.g., in non-volatile memory device is described and includes generating timing signals from the data stream so that the data stream is free from synchronization bits. The PWM data stream is converted from CML to CMOS level. An even decoder decodes the even data signal. An odd decoder decodes the odd signal. The decoders rely on the respective signal, even or odd, to increase past a slower rising signal based on both the odd and even signals to change from a default low state to a high state. The clock signal is derived from edges of the data itself.