Multiphase signal generation circuitry receives input signals that are out-of-phase with one another by a quadrature delay (e.g., 90°), and generates output signals that are out-of-phase with one another by half of the quadrature delay. A first input signal may be provided to a first delay circuitry, which is then input to a first phase interpolator. The first delay circuitry is also input to second delay circuitry, which also generates an output that is input to the first phase interpolator. The first phase interpolator outputs a first output signal. The second delay circuitry is input to third delay circuitry, which in turn is input to a second phase interpolator with a second input signal that is out-of-phase with the first input signal by the quadrature delay. The second phase interpolator outputs a second output signal that is out-of-phase with the first output signal by the half of the quadrature delay.

Multiphase signal generation circuitry receives input signals that are out-of-phase with one another by a quadrature delay (e.g., 90°), and generates output signals that are out-of-phase with one another by half of the quadrature delay. A first input signal may be provided to a first delay circuitry, which is then input to a first phase interpolator. The first delay circuitry is also input to second delay circuitry, which also generates an output that is input to the first phase interpolator. The first phase interpolator outputs a first output signal. The second delay circuitry is input to third delay circuitry, which in turn is input to a second phase interpolator with a second input signal that is out-of-phase with the first input signal by the quadrature delay. The second phase interpolator outputs a second output signal that is out-of-phase with the first output signal by the half of the quadrature delay.

A transmitter is disclosed. The transmitter includes a clock configured to generate one or more output clock signals. The transmitter further includes at least one frequency divider configured to generate a plurality of divided frequencies based on the one or more output clock signals, and a modulator. The transmitter also includes at least one antenna or transducer configured to transmit modulated data. The transmitter includes a memory configured to store instructions, and at least one processor configured to execute instructions performing operations including mapping data to a decimal code value of a plurality of decimal code values, converting the decimal code value to a shrinking base system, and selecting a set of frequencies among the plurality of divided frequencies based on the code value corresponding to the shrinking base system for the decimal code value. The modulator may be configured to modulate the decimal code value using the set of frequencies.

A transmitter is disclosed. The transmitter includes a clock configured to generate one or more output clock signals. The transmitter further includes at least one frequency divider configured to generate a plurality of divided frequencies based on the one or more output clock signals, and a modulator. The transmitter also includes at least one antenna or transducer configured to transmit modulated data. The transmitter includes a memory configured to store instructions, and at least one processor configured to execute instructions performing operations including mapping data to a decimal code value of a plurality of decimal code values, converting the decimal code value to a shrinking base system, and selecting a set of frequencies among the plurality of divided frequencies based on the code value corresponding to the shrinking base system for the decimal code value. The modulator may be configured to modulate the decimal code value using the set of frequencies.

Aspects of the disclosure provide for a method implemented by a control system for communicating with a remote device. In at least some examples, the method includes determining a frequency of operation of the remote device and determining whether the frequency of operation of the remote device varies from a programmed frequency. The method further includes determining a frequency scaling factor based on whether the frequency of operation of the remote device varies from a programmed frequency. The method further includes generating a frequency shift keying (FSK) signal, scaling the FSK signal to generate a frequency scaled shift keying (FSSK) signal, and transmitting the FSSK signal to the remote device.

A single channel receiver includes an input terminal that receives an analog input signal, a mixer that down-mixes the analog input signal by use of a phase- and/or frequency-corrected oscillator frequency signal and shifts complex-valued information contained in the analog input signal to the real part (or alternatively to the imaginary part) to obtain an intermediate real-valued analog signal, an analog-to-digital-converter that converts the intermediate analog signal into an intermediate digital signal, a demodulator that demodulates the intermediate digital signal into a digital output signal, a phase tracking loop that detects zero-crossings in the intermediate digital signal to obtain phase error information representing a phase error in the intermediate digital signal, and an oscillator that generates the phase- and/or frequency-corrected oscillator frequency signal by compensating the phase and/or frequency error in the intermediate digital signal by correcting the phase of the oscillator frequency signal with the phase error information.

Multiphase signal generation circuitry receives input signals that are out-of-phase with one another by a quadrature delay (e.g., 90°), and generates output signals that are out-of-phase with one another by half of the quadrature delay. A first input signal may be provided to a first delay circuitry, which is then input to a first phase interpolator. The first delay circuitry is also input to second delay circuitry, which also generates an output that is input to the first phase interpolator. The first phase interpolator outputs a first output signal. The second delay circuitry is input to third delay circuitry, which in turn is input to a second phase interpolator with a second input signal that is out-of-phase with the first input signal by the quadrature delay. The second phase interpolator outputs a second output signal that is out-of-phase with the first output signal by the half of the quadrature delay.

Multiphase signal generation circuitry receives input signals that are out-of-phase with one another by a quadrature delay (e.g., 90°), and generates output signals that are out-of-phase with one another by half of the quadrature delay. A first input signal may be provided to a first delay circuitry, which is then input to a first phase interpolator. The first delay circuitry is also input to second delay circuitry, which also generates an output that is input to the first phase interpolator. The first phase interpolator outputs a first output signal. The second delay circuitry is input to third delay circuitry, which in turn is input to a second phase interpolator with a second input signal that is out-of-phase with the first input signal by the quadrature delay. The second phase interpolator outputs a second output signal that is out-of-phase with the first output signal by the half of the quadrature delay.

Disclosed are techniques to compensate frequency systematic known error (FSKE) in reflector or initiator radios using a hybrid RF-digital approach in multi-carrier phase-based ranging. The hybrid RF-digital approach combines a coarse frequency compensation technique in the RF domain and a fine frequency compensation technique in the digital domain to remove the FSKE across all carrier frequencies from a device. The coarse frequency compensation performed in the RF domain may use a PLL to multiply the crystal frequency to arrive close to a target carrier frequency to compensate for a coarse portion of the known FSKE at the target frequency. The fine frequency compensation may use digital techniques to remove the remaining portion of the known FSKE not compensated by the RF. The hybrid approach reduces the number of fractional bits in the multiplier of the PLL when compared to an approach that uses only the RF-PLL to remove the FSKE.

In an embodiment a device includes a first circuit and a second circuit, wherein the first circuit is configured to generate a fourth signal and a fifth signal by applying the phase shift respectively to a first signal and to a second signal and deliver a sixth signal corresponding to a sampling over one bit of the fourth signal, a seventh signal corresponding to a sampling over one bit of the fifth signal, an eighth signal corresponding to a sampling over one bit of a difference between the fourth and fifth signals, and a ninth signal corresponding to a sampling over one bit of a sum between the fourth and fifth signals, wherein the second circuit is configured to receive the sixth, seventh, eighth, and ninth signals and determine, during a first phase where the first and second signals are representative of a first known symbol of a QPSK constellation, a state of a first bit from among a first state and a second state based on the eighth and ninth signals.