A radio receiver comprises a matched filter bank and a decision unit. The matched filter bank has a plurality of filter modules for generating correlation-strength data from a sampled radio signal, each filter module being configured to cross-correlate the sampled signal with data representing a respective filter sequence. The decision unit is configured to use the correlation-strength data to generate a sequence of decoded symbols from the sampled signal. The matched filter bank and/or decision unit are configured to determine the value of each symbol in the sequence in part based on the value of a respective earlier decoded symbol from the sequence of decoded symbols.

In accordance with an embodiment, a device configured to detect a presence of at least one digital pattern within a signal includes J memory circuits having respectively Nj memory locations; and processing circuitry comprising an accumulator configured to successively address the memory locations of the J memory circuits in a circular manner at frequency F and during an acquisition time, and successively accumulate and store values indicative of a signal intensity in parallel in the J addressed memory locations of the J memory circuits, and a detector configured to detect the possible presence of the at least one pattern.

A radio receiver comprises a matched filter bank and a decision unit. The matched filter bank has a plurality of filter modules for generating correlation-strength data from a sampled radio signal, each filter module being configured to cross-correlate the sampled signal with data representing a respective filter sequence. The decision unit is configured to use the correlation-strength data to generate a sequence of decoded symbols from the sampled signal. The matched filter bank and/or decision unit are configured to determine the value of each symbol in the sequence in part based on the value of a respective earlier decoded symbol from the sequence of decoded symbols.

A signal specification identification apparatus includes processing circuitry that estimates the transmission rate of a received signal, performs sampling frequency conversion on the received signal, calculates a probability corresponding to each of a plurality of candidates for a specification of the received signal, selects a candidate using the respective probabilities, and calculates reliability corresponding to a selected candidate, determines whether to output the selected candidate as an identification result or perform the sampling frequency conversion again, based on the reliability, and changes a parameter indicating the ratio of the sampling frequency conversion when it is determined that the sampling frequency conversion is to be performed again. Processing is repeated until the processing circuitry determines that the selected candidate as the identification result is to be output.

In accordance with an embodiment, a device configured to detect a presence of at least one digital pattern within a signal includes J memory circuits having respectively Nj memory locations; and processing circuitry comprising an accumulator configured to successively address the memory locations of the J memory circuits in a circular manner at frequency F and during an acquisition time, and successively accumulate and store values indicative of a signal intensity in parallel in the J addressed memory locations of the J memory circuits, and a detector configured to detect the possible presence of the at least one pattern.

A system and method employ an exclusive-OR gate having a first input configured to receive an RF carrier signal having an RF carrier, and a second input configured to receive a square wave signal having a square wave frequency, to output to a signal processing channel under test a binary phase shift keying (BPSK) signal comprising the RF carrier signal modulated by the square wave signal. A digital signal processor is configured to receive from the signal processing channel in-phase (I) and quadrature-phase (Q) data produced by the signal processing channel in response to the BPSK signal, and to process the I and Q data to determine an amplitude response and phase response of the signal processing channel as a function of frequency.

In one example, an apparatus includes an offset tunable edge slicer having an input to receive a pulse amplitude modulation signal. The offset tunable edge slicer also has a plurality of possible offset settings corresponding to a plurality of different reference voltages of the offset tunable edge slicer. A multiplexer has an output coupled to the input of the offset tunable edge slicer and an input to receive a control signal that selects one of the plurality of possible offset settings for the offset tunable edge slicer. A phase detector has an input coupled to an output of the offset tunable edge slicer.

Methods and systems for I/O mismatch calibration and compensation for wideband communication receivers may include receiving a radio frequency (RF) signal in a receiver of a communication device, down-sampling said received RF signal to generate a channel k and its image channel −k at baseband frequencies, determining average in-phase (I) and quadrature (Q) gain and phase mismatch of said channel k and said image channel −k, removing said average I and Q gain and phase mismatch of said channel k and said image channel −k, determining, after said removing said average I and Q gain and phase mismatch, a residual phase tilt of said channel k and said image channel −k, and compensating for said determined residual phase tilt of said channel k and said image channel −k utilizing a phase tilt correction filter.

A power transmitter (101) provides power transfer to a power receiver (105) using a wireless inductive power transfer signal. The power transmitter (101) comprises an inductor (103) generating the power transfer signal when a voltage drive signal is applied. A measurement unit (311) performs measurements of a current or voltage of the inductor (103). The measurements are performed with a time offset relative to a reference signal synchronized to the voltage drive signal. An adaptor (313) can vary the time offset to determine an optimum measurement timing offset resulting in a maximum demodulation depth which reflects a difference measure for measurements for different modulation loads of the power transfer signal. A demodulator (309) then demodulates load modulation of the inductive carrier signal from measurements with the time offset set to the optimum measurement timing offset. In some scenarios, both the timing and duration of measurements may be varied. The approach improves communication reliability.

Interfacing according to a common public radio interface in a base station in a mobile communication system is described. The interfacing comprises a conversion process for rate-converting legacy data samples. First a predetermined number of the legacy data samples is converted to frequency samples in a frequency domain, then the frequency samples are zero padded to extend the frequency range according to a related sample rate of a 4G data format and then converted into a number of data samples of the related sample rate. The related sample rate is a multiplication of S/K times a basic frame rate of the 4G data format, S samples being allocated to K frames, K and S being integers and K being 8 or less. Advantageously large buffers for allocating a large number of legacy samples to 4G frames are avoided.