Physical layer processing methods for network acquisition by remote nodes in wireless communication systems are described herein. New methods for wireless network discovery and synchronization by remote nodes are described herein that utilize spatial (e.g., antenna array) processing algorithms which may achieve enhanced functioning in challenging radio frequency environments, such as those containing interference and multipath distortion effects. These methods may include advantageous use of spatial whiteners and associated pluralities of adaptive beamformers to detect network reference and synchronization signals and estimate their parameters.

A method for Peak to Average Power Ratio (PAPR) reduction at an input of analog to digital converter (ADC) of the receiver, the method includes mapping, by a mapper, an input symbol to an output symbol that maintains a peak power constraint at the input of the ADC; wherein the mapping is responsive to (a) previously transmitted symbols and (b) a state of the channel following a transmission of the current output symbol; transmitting the output symbol by the transmitter; receiving, by the receiver, a received symbol that represents the output symbol; and de-mapping the received symbol, by a de-mapper of the receiver, to a de-mapped symbol that represents the input symbol.

A method and apparatus for generating a sampling frequency are provided. A signal is generated, of which frequency is a predetermined multiple of a reference clock, and a frequency offset in a channel is extracted from the entire frequency offset. The amount of shift is calculated by dividing the extracted frequency offset by a predetermined value, and a final sampling frequency is obtained by shifting the frequency of the generated signal by the amount of shift.

Disclosed is a receiver circuit comprising an analog-to-digital converter (ADC) circuit having an analog input, a clock input, and a digital output, and a clock divider circuit having a reference clock input and a phase selector input, and having a clock output coupled to the clock input of the ADC circuit. The clock divider circuit is configured to divide a reference clock signal coupled to the reference clock input at a reference clock frequency, to produce a clock output signal at an ADC clock frequency, at the clock output, such that the reference clock frequency is an integer multiple N of the ADC clock frequency. The clock divider circuit is further configured to select from among a plurality of selectable phases of the clock output signal, responsive to a phase selector signal applied to the phase selector input.

A cellular network includes multiple miniature base stations. The miniature base stations are communicatively connected to each other. Each one of the miniature base stations includes an antenna, a wireless signal transceiver and a digital signal processor. The antenna is arranged at a peripheral area of the miniature base stations and configured to receive and to transmit wireless signals. The wireless signal transceiver is configured to demodulate the wireless signals received from the antenna and to modulate the wireless signals transmitted by the antenna. The digital signal processor is configured to process the wireless signals, which are demodulated or modulated.

The present disclosure relates to a pre-5.sup.th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4.sup.th-Generation (4G) communication system such as Long Term Evolution (LTE). According to various embodiments of the disclosure, an apparatus of a terminal in a wireless communication system is provided. The apparatus includes at least one transceiver, and at least one processor configured to be operatively connected to the at least one transceiver, wherein the at least one processor may be configured to: obtain first synchronization of a first carrier that is in synchronization, determine second synchronization of a second carrier that is out of synchronization based on the first synchronization, and perform communication based on the second synchronization.

A cellular network includes multiple miniature base stations. The miniature base stations are communicatively connected to each other. Each one of the miniature base stations includes an antenna, a wireless signal transceiver and a digital signal processor. The antenna is arranged at a peripheral area of the miniature base stations and configured to receive and to transmit wireless signals. The wireless signal transceiver is configured to demodulate the wireless signals received from the antenna and to modulate the wireless signals transmitted by the antenna. The digital signal processor is configured to process the wireless signals, which are demodulated or modulated.

A method for Peak to Average Power Ratio (PAPR) reduction at an input of analog to digital converter (ADC) of the receiver, the method includes mapping, by a mapper, an input symbol to an output symbol that maintains a peak power constraint at the input of the ADC; wherein the mapping is responsive to (a) previously transmitted symbols and (b) a state of the channel following a transmission of the current output symbol; transmitting the output symbol by the transmitter; receiving, by the receiver, a received symbol that represents the output symbol; and de-mapping the received symbol, by a de-mapper of the receiver, to a de-mapped symbol that represents the input symbol.

The present disclosure relates to a pre-5.sup.th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4.sup.th-Generation (4G) communication system such as Long Term Evolution (LTE). According to various embodiments of the disclosure, an apparatus of a terminal in a wireless communication system is provided. The apparatus includes at least one transceiver, and at least one processor configured to be operatively connected to the at least one transceiver, wherein the at least one processor may be configured to: obtain first synchronization of a first carrier that is in synchronization, determine second synchronization of a second carrier that is out of synchronization based on the first synchronization, and perform communication based on the second synchronization.

Disclosed is a receiver circuit comprising an analog-to-digital converter (ADC) circuit having an analog input, a clock input, and a digital output, and a clock divider circuit having a reference clock input and a phase selector input, and having a clock output coupled to the clock input of the ADC circuit. The clock divider circuit is configured to divide a reference clock signal coupled to the reference clock input at a reference clock frequency, to produce a clock output signal at an ADC clock frequency, at the clock output, such that the reference clock frequency is an integer multiple N of the ADC clock frequency. The clock divider circuit is further configured to select from among a plurality of selectable phases of the clock output signal, responsive to a phase selector signal applied to the phase selector input.