H04L47/722

Controlling socket receive buffer for traffic optimization

A network device includes a network interface for establishing a communication session with another network device, a memory to store instructions, and a processor to execute the instructions. The processor may, for each time period during the communication session, adjust a size of a receive buffer of a socket. When the processor adjusts the size, the processor, if a utilization number of the receive buffer is greater than a high threshold: may determine a first new size for the receive buffer, and set a size of the receive buffer to the first new size. If the utilization number is less than a low threshold, the processor may determine a second new size for the receive buffer; and set the size of the receive buffer to the second new size.

Controlling socket receive buffer for traffic optimization

A network device includes a network interface for establishing a communication session with another network device, a memory to store instructions, and a processor to execute the instructions. The processor may, for each time period during the communication session, adjust a size of a receive buffer of a socket. When the processor adjusts the size, the processor, if a utilization number of the receive buffer is greater than a high threshold: may determine a first new size for the receive buffer, and set a size of the receive buffer to the first new size. If the utilization number is less than a low threshold, the processor may determine a second new size for the receive buffer; and set the size of the receive buffer to the second new size.

ADMISSION CONTROL OF A COMMUNICATION SESSION
20230006942 · 2023-01-05 ·

Aspects of the disclosure relate to admission control of a communication session in a network. The admission control can be implemented by a network node at the boundary of the network or a subsystem thereof. In one aspect, the admission control can be implemented during a predetermined period and can be based at least on an admission criterion, which can be specific to an end-point device, e.g., a target device or an origination device. The admission criterion can be configurable and, in certain implementations, it can be obtained from historical performance associated with establishment of communication session. Such historical performance can be assessed within a period of a configurable span.

ADMISSION CONTROL OF A COMMUNICATION SESSION
20230006942 · 2023-01-05 ·

Aspects of the disclosure relate to admission control of a communication session in a network. The admission control can be implemented by a network node at the boundary of the network or a subsystem thereof. In one aspect, the admission control can be implemented during a predetermined period and can be based at least on an admission criterion, which can be specific to an end-point device, e.g., a target device or an origination device. The admission criterion can be configurable and, in certain implementations, it can be obtained from historical performance associated with establishment of communication session. Such historical performance can be assessed within a period of a configurable span.

Generating, at least in part, and/or receiving, at least in part, at least one request

In an embodiment, an apparatus is provided that may include circuitry to generate, at least in part, and/or receive, at least in part, at least one request that at least one network node generate, at least in part, information. The information may be to permit selection, at least in part, of (1) at least one power consumption state of the at least one network node, and (2) at least one time period. The at least one time period may be to elapse, after receipt by at least one other network node of at least one packet, prior to requesting at least one change in the at least one power consumption state. The at least one packet may be to be transmitted to the at least one network node. Of course, many alternatives, modifications, and variations are possible without departing from this embodiment.

Generating, at least in part, and/or receiving, at least in part, at least one request

In an embodiment, an apparatus is provided that may include circuitry to generate, at least in part, and/or receive, at least in part, at least one request that at least one network node generate, at least in part, information. The information may be to permit selection, at least in part, of (1) at least one power consumption state of the at least one network node, and (2) at least one time period. The at least one time period may be to elapse, after receipt by at least one other network node of at least one packet, prior to requesting at least one change in the at least one power consumption state. The at least one packet may be to be transmitted to the at least one network node. Of course, many alternatives, modifications, and variations are possible without departing from this embodiment.

PROCESSING OF ETHERNET PACKETS AT A PROGRAMMABLE INTEGRATED CIRCUIT

Methods, systems, and computer programs are presented for processing Ethernet packets at a Field Programmable Gate Array (FPGA). One programmable integrated circuit includes: an internal network on chip (iNOC) comprising rows and columns; clusters, coupled to the iNOC, comprising a network access point (NAP) and programmable logic; and an Ethernet controller coupled to the iNOC. When the controller operates in packet mode, each complete inbound Ethernet packet is sent from the controller to one of the NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller. The controller is configurable to operate in quad segment interface (QSI) mode where each complete inbound Ethernet packet is broken into segments, which are sent from the controller to different NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller.

PROCESSING OF ETHERNET PACKETS AT A PROGRAMMABLE INTEGRATED CIRCUIT

Methods, systems, and computer programs are presented for processing Ethernet packets at a Field Programmable Gate Array (FPGA). One programmable integrated circuit includes: an internal network on chip (iNOC) comprising rows and columns; clusters, coupled to the iNOC, comprising a network access point (NAP) and programmable logic; and an Ethernet controller coupled to the iNOC. When the controller operates in packet mode, each complete inbound Ethernet packet is sent from the controller to one of the NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller. The controller is configurable to operate in quad segment interface (QSI) mode where each complete inbound Ethernet packet is broken into segments, which are sent from the controller to different NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller.

COMPUTE EXPRESS LINK OVER ETHERNET IN COMPOSABLE DATA CENTERS

Techniques for sending Compute Express Link (CXL) packets over Ethernet (CXL-E) in a composable data center that may include disaggregated, composable servers. The techniques may include receiving, from a first server device, a request to bind the first server device with a multiple logical device (MLD) appliance. Based at least in part on the request, a first CXL-E connection may be established for the first server device to export a computing resource to the MLD appliance. The techniques may also include receiving, from the MLD appliance, an indication that the computing resource is available, and receiving, from a second server device, a second request for the computing resource. Based at least in part on the second request, a second CXL-E connection may be established for the second server device to consume or otherwise utilize the computing resource of the first server device via the MLD appliance.

Vehicle network and method of communication

A method of communication in a vehicle network is provided. An example method includes transmitting a network allocation map in a TDMA cycle, indicating reservation of time slots in the TDMA cycle. The method further includes transmitting a synchronization signal in the TDMA cycle, to synchronize the timing of nodes in the vehicle network. Each of the reserved time slots is identified by at least a network ID of a transmitting node in the vehicle network, and a slot type comprising one of a low latency traffic slot, and a bulk traffic slot. Further, the low latency traffic slots are repeated in the TDMA cycle at least as frequently as a guaranteed QoS latency parameter. Further, the bulk traffic slots are at least as long as a guaranteed QoS throughput parameter.