An information processing method, an Ethernet switching chip and a storage medium are provided. The method includes: executing, by a master IP core, one of following operations: updating a global information table of the master IP core according to first information corresponding to the information processing request, and sending the first information to each slave IP core; updating a dedicated information table of the master IP core according to second information corresponding to the information processing request, or, sending, to a corresponding slave IP core, third information corresponding to the information processing request; or acquiring fourth information from the global information table or the dedicated information table of the master IP core based on the information processing request and sending the fourth information to a processor, or, acquiring fifth information from a corresponding slave IP core and sending the fifth information to the processor.

An information processing method, an Ethernet switching chip and a storage medium are provided. The method includes: executing, by a master IP core, one of following operations: updating a global information table of the master IP core according to first information corresponding to the information processing request, and sending the first information to each slave IP core; updating a dedicated information table of the master IP core according to second information corresponding to the information processing request, or, sending, to a corresponding slave IP core, third information corresponding to the information processing request; or acquiring fourth information from the global information table or the dedicated information table of the master IP core based on the information processing request and sending the fourth information to a processor, or, acquiring fifth information from a corresponding slave IP core and sending the fifth information to the processor.

An information processing method, an Ethernet switching chip, and a storage medium are provided. The method includes: receiving, by a master module of an Ethernet switching chip, a message information processing request, and executing, by the master module in response to the message information processing request, a self-learning operation corresponding to the message information processing request, so as to obtain a message information learning result; updating, by the master module according to the message information learning result, a message processing information table of an IP core where the master module is located; and/or, sending, by the master module, the message information learning result to a corresponding slave module, so that the corresponding slave module updates, according to the message information learning result, a message processing information table of an IP core where the slave module is located.

An information processing method, an Ethernet switching chip, and a storage medium are provided. The method includes: receiving, by a master module of an Ethernet switching chip, a message information processing request, and executing, by the master module in response to the message information processing request, a self-learning operation corresponding to the message information processing request, so as to obtain a message information learning result; updating, by the master module according to the message information learning result, a message processing information table of an IP core where the master module is located; and/or, sending, by the master module, the message information learning result to a corresponding slave module, so that the corresponding slave module updates, according to the message information learning result, a message processing information table of an IP core where the slave module is located.

Various implementations described herein refer to a device having a multi-layered logic structure with multiple layers including a first layer and a second layer arranged vertically in a stacked configuration. The device may have a first network that links nodes together in the first layer. The device may have a second network that links the nodes in the first layer together by way of the second layer so as to reduce latency related to data transfer between the nodes.

A system with co-resident data-plane and network interface controllers embodying a method for network switching of a data packet incoming from a network at a packet input processor portion of a network interface resource comprising the packet input processor, a packet output processor, and a network interface controller, implemented as a module or a single chip, to a target entity via either the network interface controller or the packet input processor is disclosed.

Systems and methods provide secure, end-to-end high-speed data encoding and communication. In certain embodiments, this is accomplished by modifying a header portion of a data packet received from a first device and complying with a one Mobile Industry Processor Interface (MIPI) protocol to create a modified data packet that complies with a faster MIPI protocol. The header portion of the modified data packet is validated during a tunnel mode operation using an error detection process to validate the modified data packet, which can then be securely transmitted to a second device that complies with the faster MIPI protocol.

Systems and methods provide secure, end-to-end high-speed data encoding and communication. In certain embodiments, this is accomplished by modifying a header portion of a data packet received from a first device and complying with a one Mobile Industry Processor Interface (MIPI) protocol to create a modified data packet that complies with a faster MIPI protocol. The header portion of the modified data packet is validated during a tunnel mode operation using an error detection process to validate the modified data packet, which can then be securely transmitted to a second device that complies with the faster MIPI protocol.

Methods and various structures provide for loopback tuning, testing, and calibrating of a transceiver, including: supplying RF drive to both a transmitter and a receiver of the transceiver from one oscillator; applying a modulation waveform to a transceiver block of the transceiver to produce an amplitude-modulated signal; converting a sideband of the amplitude-modulated signal to a baseband signal having a frequency suitable for processing by a receiver digital block, where processing the baseband signal produces a digital output; and performing tuning, testing, and calibrating of the transceiver block, based at least in part on the digital output.

A system for processing messages of a high rate data stream and an apparatus including: a message processor including a plurality of processor sub-modules and configured to read an input data stream, process the input data stream, and to output an output data stream; at least one payload memory storing data related to the input data stream and accessible to the message processor; at least one instruction memory accessible to the message processor and storing computer program instructions configuring the message processor to process the input data stream; and an application processor configured to rewrite the at least one instruction memory.