A network switch includes a field programmable gate array (FPGA) and a processor. The FPGA is configured to transfer a processing target packet to a transfer destination, based on transfer definition information, and to transfer a copy of the processing target packet to the processor. The processor is configured to delete an entry of the transfer definition information based on a transfer record information, and to update the transfer record information based on the copy of the processing target packet.

The subject matter disclosed herein relates to a frame switch of an AFDX network in which the data acquisition application is decentralized. When the switch has to acquire the data transmitted on a virtual link, the switching table contains, apart from the input port and the output port (s) taken by this link, an ID representing the MAC address of the switch. The frames of this link are then not only switched but also transmitted to the network interface of the switch and processed by a dedicated application (DDA), hosted inside the switch. This application can be interrogated by a remote server and transfer the data that it has stored locally.

A network switch includes a field programmable gate array (FPGA) and a processor. The FPGA is configured to transfer a processing target packet to a transfer destination, based on transfer definition information, and to transfer a copy of the processing target packet to the processor. The processor is configured to delete an entry of the transfer definition information based on a transfer record information, and to update the transfer record information based on the copy of the processing target packet.

A method and a first device (110) of a switched network (100), for managing data frames received, at a first port, from a second device (120) are disclosed. The first device (110) handles the first port and a second port for transfer of data frames between the first and second devices (110, 120). The first device (110) is addressable by a Media Access Control address, “MAC address”, associated with the first port. The first device (110) receives (201), from the second device (120), at least one data frame at the second port. The first device (110) sends (202), on the first port, a message including the MAC address associated with the first port.

One embodiment of the present invention provides a system for facilitating synchronization of MAC addresses in a fabric switch. During operation, the system divides a number of media access control (MAC) addresses associated with devices coupled to an interface of the switch. The system then computes a checksum for a respective chunk of MAC addresses. In addition, the system broadcasts MAC address information of the chunk to facilitate MAC address synchronization in a fabric switch of which the switch is a member, and to manage the chunks and their corresponding checksum, thereby correcting an unsynchronized or race condition in the fabric switch.

One embodiment of the present invention provides a switch. During operation, the switch parses a first schema of the switch. The first schema indicates initialization information for one or more services of the switch expressed based on one or more tags. The switch then identifies a tag of the one or more tags in the first schema based on the parsing and identifies information corresponding to the tag from a profile of the switch. Subsequently, the switch generates a second schema from the first schema based on the identified information.

System and method for supporting scalable representation of switch port status in a high performance computing environment. In accordance with an embodiment, a scalable representation of switch port status can be provided. By adding a scalable representation of switch port status at each switch (both physical and virtual)—instead of getting all switch port changes individually, the scalable representation of switch port status can combine a number of ports that can scale by just using a few bits of information for each port's status.

System and method for supporting configurable legacy P_Key table abstraction using a bitmap based hardware implementation in a high performance computing environment. A mapping table in DRAM can be provided through the use of a software based SMA that implements the mapping table. With this mapping table, it is possible to provide a legacy compliant view of a bit map based P_Key table. Such a legacy compliant view can be called a virtual P_Key table, or a configurable legacy P_Key table abstraction.

System and method for supporting node role attributes in a high performance computing environment. In accordance with an embodiment, a node role attribute can comprise a vendor defined subnet management attribute. When a subnet manager attempts to discover a high performance computing environment, such as an InfiniBand subnet, or a switch topology, identifying a topology is quite complex when subnet manager can only observe connectivity, without context behind the connectivity (the roles of the different nodes in the connectivity). However, when a subnet has a node role attribute enabled, the subnet manager can map the interconnect more effectively as it can discover not only the connectivity during the initial sweep, but it can also discover the role of each node discovered, thus leading to a more efficient interconnect discovery.

System and method for supporting scalable representation of switch port status in a high performance computing environment. In accordance with an embodiment, a scalable representation of switch port status can be provided. By adding a scalable representation of switch port status at each switch (both physical and virtual)—instead of getting all switch port changes individually, the scalable representation of switch port status can combine a number of ports that can scale by just using a few bits of information for each port's status.