One embodiment describes a network system. The system includes a primary enclosure including a network switch system that includes a plurality of physical interface ports. A first one of the plurality of physical interface ports is to communicatively couple to a network. The system further includes a sub-enclosure comprising a network interface card (NIC) to which a computer system is communicatively coupled and a downlink extension module (DEM) that is communicatively coupled with the NIC and a second one of the plurality of physical interface ports of the network switch system to provide network connectivity of the computer system to the network via the network switch system.

One embodiment describes a network system. The system includes a primary enclosure including a network switch system that includes a plurality of physical interface ports. A first one of the plurality of physical interface ports is to communicatively couple to a network. The system further includes a sub-enclosure comprising a network interface card (NIC) to which a computer system is communicatively coupled and a downlink extension module (DEM) that is communicatively coupled with the NIC and a second one of the plurality of physical interface ports of the network switch system to provide network connectivity of the computer system to the network via the network switch system.

A switch-connected dragonfly network and method of operating. A plurality of groups of row switches is organized according to multiple rows and columns, each row including multiple groups of row switches connected to form a two-level dragonfly network. A plurality of column switches interconnect groups of row switches along respective columns, a column switch associated with a corresponding group of row switches in a row. A switch port with a same logical port on a row switch at a same location in each group along the respective column connects to a same column switch. The switch-connected dragonfly network is expandable by adding additional rows, an added row comprising a two-level dragonfly network. A switch group of said added row associated with a column being connects to an available port at an existing column switch of said column by corresponding added S path link with no re-cabling of the switched network required.

This invention is related to an Express Traversal (EXTRA) Network on Chip (NoC) comprising a number of EXTRA routers. The EXTRA NoC comprises a Buffer Write and Route Computation (BW/RC) pipeline, a Switch Allocation-Local (SA-L) pipeline, a Setup Request (SR) pipeline, a Switch Allocation-Global (SA-G) pipeline, and a Switch Traversal and Link Traversal (ST/LT) pipeline. The BW/RC pipeline is configured to write an incoming flit to an input buffer(s) of a start EXTRA router and compute the route for the incoming head flit by selecting an output port to depart from the start EXTRA router. The SA-L pipeline is configured to arbitrate the start EXTRA router to choose an input port and an output port for a winning flit. The SR pipeline is configured to handle the transmission of a number of SR signals from the start EXTRA router to downstream EXTRA routers.

A system and method of transferring cells through a switch fabric having a shared memory crossbar switch, a plurality of cell receive blocks and a plurality of cell transmit blocks. The system determines, based on a number of cells queued up in respective output buffers in the cell transmit blocks, output buffers in the cell transmit blocks that can receive cells on a low latency path. The cells transferred include first cells that can be transferred on the low latency path and second cells that cannot be transferred via the low latency path. The first cells are transferred via a bypass mechanism in shared memory to the output buffers. The second cells are transferred by writing the second cells to shared memory, reading the second cells from shared memory and transferring the second cells read from shared memory to the output buffers in the cell transmit blocks.

Described are embodiments of methods, apparatuses, and systems for multi-protocol tunneling across a multi-protocol I/O interconnect of computer apparatus. A multi-protocol I/O interconnect may include a switching fabric operatively coupled to a first protocol-specific controller and a second protocol-specific controller, and may be configured to simultaneously route packets of the first protocol to the first protocol-specific controller and packets of the second protocol to the second protocol-specific controller. Other embodiments may be described and claimed.

One embodiment describes a network system. The system includes a primary enclosure including a network switch system that includes a plurality of physical interface ports. A first one of the plurality of physical interface ports is to communicatively couple to a network. The system further includes a sub-enclosure comprising a network interface card (NIC) to which a computer system is communicatively coupled and a downlink extension module (DEM) that is communicatively coupled with the NIC and a second one of the plurality of physical interface ports of the network switch system to provide network connectivity of the computer system to the network via the network switch system.

Many network protocols, including certain Ethernet protocols, include specifications for multiplexing using of virtual lanes. Due to skews and/or other uncertainties associated with the process, packets from virtual lanes may arrive at the receiver out of order. The present disclosure discusses implementations of receivers that may use multiplexer based crossbars, such as Clos networks, to reorder the lanes. State-based controllers for the Clos networks and state-based methods to assign routes in are also discussed.

This invention is related to an Express Traversal (EXTRA) Network on Chip (NoC) comprising a number of EXTRA routers. The EXTRA NoC comprises a Buffer Write and Route Computation (BW/RC) pipeline, a Switch Allocation-Local (SA-L) pipeline, a Setup Request (SR) pipeline, a Switch Allocation-Global (SA-G) pipeline, and a Switch Traversal and Link Traversal (ST/LT) pipeline. The BW/RC pipeline is configured to write an incoming flit to an input buffer(s) of a start EXTRA router and compute the route for the incoming head flit by selecting an output port to depart from the start EXTRA router. The SA-L pipeline is configured to arbitrate the start EXTRA router to choose an input port and an output port for a winning flit. The SR pipeline is configured to handle the transmission of a number of SR signals from the start EXTRA router to downstream EXTRA routers.

A routing node includes: at least one optical buffer, a switching node, and at least one transmission waveguide, where an output end of each optical buffer is connected to an input end of the switching node; each transmission waveguide is connected to an output end of the switching node. The optical buffer is configured to parse a received optical signal to obtain an identifier of a destination routing node, and send the identifier to the switching node. The switching node determines whether an output port required by the destination routing node is in an idle state or a busy state; and control the optical buffer to store the optical signal if the output port is in a busy state; or send the optical signal to the destination routing node if the output port is in an idle state.