Patent classifications
H04L49/508
Overload protection engine
A fabric interface, including: an ingress port to receive incoming network traffic; a host interface to forward the incoming network traffic to a host; and a virtualization-aware overload protection engine including: an overload detector to detect an overload condition on the incoming network traffic; a packet inspector to inspect packets of the incoming network traffic; and a prioritizer to identify low priority packets to be dropped, and high priority packets to be forwarded to the host.
Packet Forwarding Method and Apparatus
Embodiments of the present invention disclose a packet forwarding method and apparatus. The method includes: receiving, by a first scheduler, a target packet; sending the target packet to a destination physical egress port corresponding to the egress port information, and increasing, according to the queue identifier, a queue length of a virtual queue corresponding to the queue identifier by the packet length; sending update information to a second scheduler, where the update information includes that the queue length of the virtual queue is increased by the packet length; and decreasing the queue length of the virtual queue by the packet length according to a bandwidth scheduling result that is corresponding to the update information and sent by the second scheduler. In this way, even if back pressure appears in the destination physical egress port corresponding to the target packet, that the first scheduler sends the target packet is not affected.
Signalling congestion
Congestion in respect to a network element operable to forward data items in a telecommunications networks, and in respect to a processing element operable to process requests for service is signaled. In either, the element is operable to perform its processing function at up to a processing rate which is subject to variation, and has a queue for items awaiting processing having a counter associated therewith which maintains a count from which a queue metric is derivable. A method comprises: updating the count at a rate dependent on the processing rate; further updating the count in response to receipt of items awaiting processing; and signalling a measure of congestion in respect of the element in dependence on the queue metric; then altering the rate at which the count is being updated and adjusting the counter whereby to cause a change in the queue metric if the processing rate has changed.
HARDWARE ACCELERATION TECHNIQUES USING FLOW SELECTION
In some embodiments, a method receives a packet for a flow associated with a workload. Based on an indicator for the flow, the method determines whether the flow corresponds to one of an elephant flow or a mice flow. Only when the flow is determined to correspond to an elephant flow, the method enables a hardware acceleration operation on the packet. The hardware acceleration operation may include hardware operation offload, receive side scaling, and workload migration.
Turn-based deadlock-free routing in a Cartesian topology
An apparatus includes an interface and a processor. The interface communicates with a network including network elements interconnected in a Cartesian topology. The processor defines first and second groups of turns, each turn includes a hop from a previous network element to a current network element and a hop from the current network element to a next network element. Based on the turns, the processor specifies rules that when applied to packets traversing respective network elements, guarantee that no deadlock conditions occur in the network. The rules for a given network element include (i) forwarding rules to reach a given target without traversing the turns of the second group, and (ii) Virtual Lane (VL) modification rules for reassigning packets, which traverse turns of the first group and which are assigned to a first VL, to a different second VL. The processor configures the given network element with the rules.
Turn-based deadlock-free routing in a Cartesian topology
An apparatus includes an interface and a processor. The interface communicates with a network including network elements interconnected in a Cartesian topology. The processor defines first and second groups of turns, each turn includes a hop from a previous network element to a current network element and a hop from the current network element to a next network element. Based on the turns, the processor specifies rules that when applied to packets traversing respective network elements, guarantee that no deadlock conditions occur in the network. The rules for a given network element include (i) forwarding rules to reach a given target without traversing the turns of the second group, and (ii) Virtual Lane (VL) modification rules for reassigning packets, which traverse turns of the first group and which are assigned to a first VL, to a different second VL. The processor configures the given network element with the rules.
APPARATUS, SYSTEM, AND METHOD OF OUT-OF-ORDER DELIVERY OF WIRELESS COMMUNICATION FRAMES
For example, a wireless communication station (STA) may be configured to determine whether a stream of frames is suitable for out-of-order delivery from a first Medium Access Control layer (MAC-layer) process to a second MAC-layer process, the second MAC-layer process is above the first MAC-layer process; and, based on a determination that the stream of frames is suitable for out-of-order delivery, to deliver to the second MAC-layer process one or more frames of the stream of frames according to an out-of-order delivery scheme.
Network data processor having per-input port virtual output queues
Various embodiments of a virtual output queue system within a network element enables per-input port virtual output queues within a network data processor of the network element. In one embodiment, each port managed by a network data processor has an associated set of virtual output queues for each output port on the network data element. In one embodiment, network data processor hardware supports per-processor VOQs and per-input port VOQs are enabled in hardware for layer 3 forwarding by overloading layer 2 forwarding logic. In such embodiment, a mapping table is generated to enable virtual per-input port VOQs for layer 3 forwarding logic using layer 2 logic that is otherwise unused during layer 3 forwarding. In one embodiment, multiple traffic classes can be managed per-input port when using per-input port VOQs. In one embodiment, equal cost multi-path (ECMP) and link aggregation support is also enabled.
End to end flow control
A network device implementing the subject system for end to end flow control may include at least one processor circuit that may be configured to detect that congestion is being experienced by at least one queue of a port and identify another network device that is transmitting downstream traffic being queued at the at least one queue of the port that is at least partially causing the congestion. The at least one processor circuit may be further configured to generate an end to end flow control message that comprises an identifier of the port, the end to end flow control message indicating that the downstream traffic should be flow controlled at the another network device. The at least one processor circuit may be further configured to transmit, out-of-band and through at least one intermediary network device, the end to end flow control message to the another network device.
Hardware acceleration techniques using flow selection
In some embodiments, a method receives a packet for a flow associated with a workload. Based on an indicator for the flow, the method determines whether the flow corresponds to one of an elephant flow or a mice flow. Only when the flow is determined to correspond to an elephant flow, the method enables a hardware acceleration operation on the packet. The hardware acceleration operation may include hardware operation offload, receive side scaling, and workload migration.