Patent classifications
H04L49/9031
HIGH THROUGHPUT INGRESS DATAPATH FOR A VIRTUAL MACHINE
Some embodiments provide a method of forwarding data messages to a machine that executes on a host computer and has an associated virtual network interface controller (VNIC) also executing on the host computer. The method retrieves data messages from a queue associated with the VNIC and stores these data messages in a first set of buffer data stores associated with the VNIC. When the first buffer set reaches a threshold congestion level, the method stores data messages subsequently retrieved from the VNIC queue in a second set of buffer data stores associated with the VNIC. In some embodiments, a set of one or more processes executing on the machine retrieves the data messages stored in the buffer sets for processing by these processes or other processes.
Circular queue management with split indexes
Methods and apparatus for managing circular queues are disclosed. A pointer designates an index position of a particular queue element and contains an additional pointer state, whereby two pointer values (split indexes) can designate the same index position. Front and rear pointers are respectively managed by dequeue and enqueue logic. The front pointer state and rear pointer state distinguish full and empty queue states when both pointers designate the same index position. Asynchronous dequeue and enqueue operations are supported, no lock is required, and no queue entry is wasted. Hardware and software embodiments for numerous applications are disclosed.
Remote direct memory access based networking gateway
A system includes a memory including a plurality of rings, an endpoint associated with a ring of the plurality of rings, and a gateway. The gateway is configured to receive a notification from the endpoint regarding a packet made available in the ring associated with the endpoint, access the ring with an RDMA read request, retrieve the packet made available in the ring, and forward the packet on an external network.
Systems and methods for providing lockless bimodal queues for selective packet capture
In a network system, an application receiving packets can consume one or more packets in two or more stages, where the second and the later stages can selectively consume some but not all of the packets consumed by the preceding stage. Packets are transferred between two consecutive stages, called producer and consumer, via a fixed-size storage. Both the producer and the consumer can access the storage without locking it and, to facilitate selective consumption of the packets by the consumer, the consumer can transition between awake and sleep modes, where the packets are consumed in the awake mode only. The producer may also switch between awake and sleep modes. Lockless access is made possible by controlling the operation of the storage by the producer and the consumer both according to the mode of the consumer, which is communicated via a shared memory location.
System for controlling data flow between multiple processors
First and second processors that are in communication with each other are disclosed. The first processor includes a sampling controller, a sampling circuit, and a data flow controller. The sampling controller is configured to receive multiple identifiers and corresponding enable signals associated with data that is to be transmitted to or received from the second processor, and generate an identification signal and a sampling signal based on one of the identifiers and the corresponding enable signal. The sampling circuit is configured to sample multiple data counts to generate corresponding sampled counts based on the identification signal and the sampling signal. The data flow controller is configured to generate a control signal based on the identifiers, the corresponding enable signals, the data counts, and the corresponding sampled counts to control data flow between the first and second processors.
SYSTEMS AND METHODS FOR PROVIDING LOCKLESS BIMODAL QUEUES FOR SELECTIVE PACKET CAPTURE
In a network system, an application receiving packets can consume one or more packets in two or more stages, where the second and the later stages can selectively consume some but not all of the packets consumed by the preceding stage. Packets are transferred between two consecutive stages, called producer and consumer, via a fixed-size storage. Both the producer and the consumer can access the storage without locking it and, to facilitate selective consumption of the packets by the consumer, the consumer can transition between awake and sleep modes, where the packets are consumed in the awake mode only. The producer may also switch between awake and sleep modes. Lockless access is made possible by controlling the operation of the storage by the producer and the consumer both according to the mode of the consumer, which is communicated via a shared memory location.
System and method to deter software tampering using interlinked sub-processes
A method is disclosed for deterring the reverse engineering of computer software code. The method involves the recognition of an unauthorized access attempt by one of a plurality of linked sub-processes embedded in the computer software code. In response to the unauthorized attempt, each of the sub-processes begins a recursive execution, resulting in computer system resources being increasingly diverted to the linked sub-processes, making it difficult to continue unauthorized attempts to access the computer software code.
ROUTERLESS NETWORKS-ON-CHIP
The disclosed technology concerns methods, apparatus, and systems for designing and generating networks-on-chip (“NoCs”), as well as to hardware architectures for implementing such NoCs. The disclosed NoCs can be used, for instance, to interconnect cores of a chip multiprocessor (aka a “multi-core processor”). In one example implementation, a wire-based routerless NoC design is disclosed that uses deterministically specified wire loops to connect the cores of the chip multiprocessor. The disclosed technology also comprises network interface architectures for use in an NoC. For example, a core can be equipped with a low-area-cost interface that is deadlock-free, uses buffering sharing, and provides low latency.
Rate limiter for a message gateway
A hardware-implemented rate limiter is described. This implementation guarantees that messages containing a value v are not forwarded at a higher rate than a predefined threshold value r. More specifically, given a number of times x in a time interval y, which specifies a rate r defined by x/y, the rate limiter reports a violation by selectively setting an error value when v occurs more than x times during the time interval y. Moreover, the rate limiter may be able to keep track of multiple predefined threshold values for different rates. Furthermore, the rate limiter may keep track of 2.sup.b different values v, where b is the number of digits of the binary representation of v.
Apparatus and method for performing InfiniBand communication between user programs in different apparatuses
In InfiniBand, communication is made between a first queue-pair (QP) allocated to a first user-program executed within a first apparatus and a second QP allocated to a second user-program executed within a second apparatus. The first apparatus sets a specific code to a send work-request, after moving information previously set to the send work-request to a portion of the data, and transmits the data added with a first QP number identifying the first QP to the second apparatus. The second apparatus determines that the received data is added with the QP number, when the specific code is set to a receive work-request, identifies the first user-program based on the QP number, and sends the data to the second user-program via the receive work-request after deleting the QP number from the data and moving information stored in the portion of the data to the receive work-request.