A method for data transmission may be implemented on an electronic device having one or more processors. The one or more processors may include a master queue including a master queue head and a plurality of primary ports that are connected to each other using a serial link. The method may include operating the master queue head to obtain a message. The method may also include operating the master queue head to segment the message into a plurality of segments. The method may also include operating the master queue head to transmit the plurality of segments to a first primary port of the plurality of primary ports in the master queue. The method may also include operating the first primary port to transmit the plurality of segments to a second primary port of the plurality of primary ports in the master queue.

A peripheral device coupled to a host includes a network interface, a packet processor, and a Data Processing Unit (DPU). The packet processor receives from a communication network, via the network interface, packets that originated from a source in an original order and received at the peripheral device in as order different from the original order. The packet processor splits the received packets into headers and payloads, sends the payloads for storage in a host memory and sends the headers without the payloads for storage in a DPU memory, and based on the headers produces a hint indicative of processing to be applied to the headers, by the DPU, for identifying the original order. Based on the hint, the DPU identifies the original order of the packets by applying the processing indicated by the hint to respective headers in the DPU memory, and notifies the host of the original order.

The packet processing system, according to an example embodiment, comprises a Network Interface Controller (NIC) to receive and transmit network packets; a memory unit for storing network packets; a processor for processing network packets stored in the memory unit; a cache unit to access all data to the processor from the memory unit; and an application process running on the processing unit. The NIC includes a packet processing means to process the network packets received by the NIC. The packet processing means includes a Contiguous Header Mapping/Map (CHM) header-data splitter to split said network packets into a header portion and a payload portion; a table or equivalent to store the contiguous header-data split configuration data; and a packet Direct Memory Access (DMA) unit to DMA copy said header portion and said payload portion into separate memory area/location and contiguously map said header portion of network packets in the memory unit.

A method includes obtaining a first plurality of encrypted traffic flows traversing a communication network, performing a first classification, wherein a result of the first classification identifies a traffic type associated with each encrypted traffic flow of the first plurality of encrypted traffic flows, and wherein the first classification is based on a traffic pattern of the each encrypted traffic flow, performing a second classification, wherein a result of the second classification identifies a traffic type associated with each server name indication from which the first plurality of encrypted traffic flows is associated, and wherein the second classification is based on the result of the first classification, and performing a third classification identifying a traffic type associated with each encrypted traffic flow of the first plurality of encrypted traffic flows, wherein the third classification is based on a combination of the results of the first classification and the second classification.

In one embodiment, a system includes a peripheral device including a memory access interface to receive from a host device headers of packets, while corresponding payloads of the packets are stored in a host memory of the host device, and descriptors being indicative of respective locations in the host memory at which the corresponding payloads are stored, a data processing unit memory to store the received headers and the descriptors without the payloads of the packets, and a data processing unit to process the received headers, wherein the peripheral device is configured, upon completion of the processing of the received headers by the data processing unit, to fetch the payloads of the packets over the memory access interface from the respective locations in the host memory responsively to respective ones of the descriptors, and packet processing circuitry to receive the headers and payloads of the packets, and process the packets.

A method includes obtaining a first plurality of encrypted traffic flows traversing a communication network, performing a first classification, wherein a result of the first classification identifies a traffic type associated with each encrypted traffic flow of the first plurality of encrypted traffic flows, and wherein the first classification is based on a traffic pattern of the each encrypted traffic flow, performing a second classification, wherein a result of the second classification identifies a traffic type associated with each server name indication from which the first plurality of encrypted traffic flows is associated, and wherein the second classification is based on the result of the first classification, and performing a third classification identifying a traffic type associated with each encrypted traffic flow of the first plurality of encrypted traffic flows, wherein the third classification is based on a combination of the results of the first classification and the second classification.

Methods, apparatus, and processor-readable storage media for securing data transmissions using split messages are provided herein. An example computer-implemented method includes obtaining a plurality of messages including content to be transmitted from a host device to at least one storage system; dividing each of the plurality messages into two or more corresponding parts; and transmitting (i) a set of packets comprising the content over one or more communication channels, wherein the two or more corresponding parts of two or more of the plurality of messages are transmitted in different packets of the set, and (ii) information for reassembling the plurality of messages from the packets, wherein the information is identified using a mechanism specific to the at least one storage system.

A transmission device includes N wireless transmission circuits and N transmission buffers. N is an integer equal to or greater than two. Each of the N transmission buffers is connected to a respective wireless transmission circuit of the N wireless transmission circuits. At least a part of a piece of delivery data is stored in each of the N transmission buffers before the N wireless transmission circuits establish wireless links. The N wireless transmission circuits are instructed to transmit the piece of delivery data stored in the N transmission buffers after the N wireless transmission circuits establish the wireless links.

In a packet processing method, a network device receives a packet of an application running in a server connected to the network device. The network device separates data of the application from the packet, and writes the data of the application into a memory allocated in the server to the application.

A first memory device stores (i) a head part of a FIFO queue structured as a linked list (LL) of LL elements arranged in an order in which the LL elements were added to the FIFO queue and (ii) a tail part of the FIFO queue. A second memory device stores a middle part of the FIFO queue, the middle part comprising a LL elements following, in an order, the head part and preceding, in the order, the tail part. A queue controller retrieves LL elements in the head part from the first memory device, moves LL elements in the middle part from the second memory device to the head part in the first memory device prior to the head part becoming empty, and updates LL parameters corresponding to the moved LL elements to indicate storage of the moved LL elements changing from the second memory device to the first memory device.