Patent classifications
H04L49/9094
Packet processing at a server
A server processers received real-time transport protocol packets from a first device to obtain sequentially ordered packets at a first buffer. The server decodes the sequentially ordered packets to obtain decoded packets at a decoder. The server encodes the decoded packets to obtain encoded packets at an encoder. The server transmits the encoded packets from the encoder to a storage unit. The server fetches the encoded packets from the storage unit at a first interval using a second buffer. The server transmits the encoded packets from the second buffer to a second device at a second interval.
Apparatus for buffered transmission of data
An apparatus with a data input, a data output, a first buffer, a second buffer, and control logic is disclosed. The control logic is equipped to route data packets that are received through the data input to the first buffer or the second buffer and to flag them as valid or invalid, and to provide data packets that are to be output through the data output from the first buffer or the second buffer, equipped to provide a data packet that is to be output through the data output from the first buffer when the data packet is being written into the first buffer at the time of a start of the readout, to provide it from the second buffer when the data packet is being written into the second buffer at the time of a start of the readout.
Packet value based packet processing
Embodiments of the invention include methods for handling packets in a communications network. In one embodiment, a method is implemented in an electronic device. The method includes at a first end of a queue in the electronic device, determining admission of a first packet to the first end of the queue based on a length of the first packet, where when the admission of the first packet would cause the queue to become full, the admission is further based on a packet value of the first packet and a data structure tracking packet value distribution of packets in the queue. The method further includes at a second end of the queue, dropping a second packet from the second end of the queue when the second packet's corresponding packet value is marked as to be dropped in the data structure upon admitting packets to the first end of the queue.
Method and system for reliable and deterministic data transmission
The present invention relates to a data transmission system including a data exchange unit; wherein, to transmit a data frame, it passes successively at least through an interface module that is configured to receive said data frame from outside the transmission system; an analysis and filtering module responsible for processing said data frame which is received from the interface module before encapsulation; and an encapsulation module responsible for encapsulating said data frame processed by the analysis and filtering module, wherein two successive modules through which said data frame passes are connected to one another by an interconnection device each including a temporary memory for storing said frame and the read and write accesses to said memory being frequency-independent.
Digital signal processor/network synchronization
A system for synchronizing a local audio processing clock rate of a digital signal processor (DSP) to an audio clock rate of a network to which the DSP is connected. The system includes an adjustable clock synthesizer that is configured to establish the local audio processing clock rate of the DSP. The DSP is configured to generate events that are associated with the local audio processing clock rate of the DSP. The DSP is further configured to monitor the generated events over time and based on the monitored events cause the adjustable clock synthesizer to adjust the local audio processing clock rate of the DSP to better match the network audio clock rate.
Digital Signal Processor/Network Synchronization
A system for synchronizing a local audio processing clock rate of a digital signal processor (DSP) to an audio clock rate of a network to which the DSP is connected. The system includes an adjustable clock synthesizer that is configured to establish the local audio processing clock rate of the DSP. The DSP is configured to generate events that are associated with the local audio processing clock rate of the DSP. The DSP is further configured to monitor the generated events over time and based on the monitored events cause the adjustable clock synthesizer to adjust the local audio processing clock rate of the DSP to better match the network audio clock rate.
RELIABLE TRANSPORT OFFLOADED TO NETWORK DEVICES
Examples described herein relate to offload reliable transport management to a network interface device and store packets to be resent, based on received packet receipt acknowledgements (ACKs), into one or more kernel space queues that are also accessible in user space.
TRANSMITTING DEVICE, RECEIVING DEVICE, PACKET TRANSFER SYSTEM,PACKET TRANSFER METHOD, AND PACKET TRANSFER PROGRAM
A transmission device (10) includes a flow table (11) that stores identification information about an uninterruptible target flow; a transmission-side identification unit (12) that identifies whether a received packet is from the target flow or a non-target flow based on whether the received packet matches the identification information about the target flow stored in the flow table (11); a tag application unit (13) that applies, to packets from the target flow, an uninterruptible identifier indicating that the packets are from the target flow and a sequence number for distinguishing the packets from other packets; and a branch unit (14) that branches the packets from the target flow processed by the tag application unit (13) into packets to be transferred to an active path (41) among redundant routes and packets to be transferred to a backup path (42) among the redundant routes.
TRANSPORT CONTROL WORD ARCHITECTURE FOR PHYSICAL PORT MIRRORING
Aspects include receiving, at an input/output (I/O) processor, a transport control word (TCW) that includes an instruction to perform physical port mirroring. It is identified, by the I/O processor, a first port to be mirrored and a second port to perform the mirroring. The second port is a physical port on a host bus adapter (HBA). In response to outbound data being sent to the first port for transmission to a first target device and to the instruction specifying outbound port mirroring, the I/O processor sends a copy of the outbound data to a second target device via the second port. In response to receiving inbound data at the first port and to the instruction specifying inbound port mirroring, a copy of the inbound data is transmitted to the second target device via the second port.
Switch for transmitting packet, network on chip having the same, and operating method thereof
A Network-on-Chip (NoC) includes a packet transmission switch, and a corresponding method of operating the NoC includes storing packets received from an input terminal in a buffer, storing buffer locations in which each of the packets is stored in an ordering queue of an output terminal, and sequentially outputting the packets from the output terminal according to the buffer locations.