A physical layer transceiver, for connecting a host device to a wireline channel medium in which a signal component occurring at a particular time may cause interference at other times, includes a host interface for coupling to a host device, a line interface for coupling to the channel medium, and filter circuitry operatively coupled to the line interface to filter the interference caused by the signal component at the particular time and at the one or more other times. The filter circuitry includes at least one filter segment configured to operate at a first rate derived from a channel operating frequency to filter the signal component at the particular time, and at least one respective filter segment configured to operate at a respective additional rate different from the first rate. Respective delay elements allow each respective filter segment to filter the signal component at a one of the other times.

A physical layer transceiver, for connecting a host device to a wireline channel medium in which a signal component occurring at a particular time may cause interference at other times, includes a host interface for coupling to a host device, a line interface for coupling to the channel medium, and filter circuitry operatively coupled to the line interface to filter the interference caused by the signal component at the particular time and at the one or more other times. The filter circuitry includes at least one filter segment configured to operate at a first rate derived from a channel operating frequency to filter the signal component at the particular time, and at least one respective filter segment configured to operate at a respective additional rate different from the first rate. Respective delay elements allow each respective filter segment to filter the signal component at a one of the other times.

Methods, systems, and devices for wireless communications are described. A device (e.g., a base station or a user equipment (UE)) may identify a sequence length corresponding to a number of resource blocks, and select a modulation scheme based on the sequence length. The device may select, from a set of sequences associated with the modulation scheme, a sequence having the sequence length. In some examples, the set of sequences may include at least one of a set of time domain phase shift keying computer-generated sequences or a set of frequency domain phase shift keying computer-generated sequences. The device may generate a reference signal for a data transmission based on the sequence and transmit the reference signal within the number of resource blocks.

A signal is transmitted at a high speed in a direction opposite to a transmitting direction of a main large-capacity channel. A first transmitting unit transmits a first signal including a clock component to an external device through a transmission path as a differential signal. A second transmitting unit superimposes a second signal including a clock component on the transmission path as an in-phase signal to transmit to the external device. A state notifying unit communicates with the external device through a pair of differential transmission paths included in the transmission path and notifies the external device of a connection state of its own device by a DC bias potential of at least one of the pair of differential transmission paths.

A signal is transmitted at a high speed in a direction opposite to a transmitting direction of a main large-capacity channel. A first transmitting unit transmits a first signal including a clock component to an external device through a transmission path as a differential signal. A second transmitting unit superimposes a second signal including a clock component on the transmission path as an in-phase signal to transmit to the external device. A state notifying unit communicates with the external device through a pair of differential transmission paths included in the transmission path and notifies the external device of a connection state of its own device by a DC bias potential of at least one of the pair of differential transmission paths.

A data compressor a zero-value remover, a zero bit mask generator, a non-zero values packer, and a row-pointer generator. The zero-value remover receives 2.sup.N bit streams of values and outputs 2.sup.N non-zero-value bit streams having zero values removed from each respective bit stream. The zero bit mask generator receives the 2.sup.N bit streams of values and generates a zero bit mask for a predetermined number of values of each bit stream in which each zero bit mask indicates a location of a zero value in the predetermined number of values corresponding to the zero bit mask. The non-zero values packer receives the 2.sup.N non-zero-value bit streams and forms a group of packed non-zero values. The row-pointer generator that generates a row-pointer for each group of packed non-zero values.

Certain aspects of the present disclosure provide techniques for channel estimation for two-stage sidelink control using sidelink data channel demodulation reference signals (DMRS). A user equipment (UE) can transmit DMRS for the sidelink data channel. The UE may transmit the second stage of the sidelink control using antenna ports or a precoder used for the sidelink data channel. The receiving device may receive the DMRS, estimate the channel, and demodulate the second stage of the sidelink control based on the estimated channel. The receiving device may flexibly determine the DMRS to use for the estimation and demodulation.

A terminal is disclosed including a transmitter that transmits uplink control information and uplink data using an uplink shared channel; and a processor that, if frequency hopping is applied to the uplink shared channel, determines a mapping position for the uplink control information for each hop of the frequency hopping. In other aspects, a radio communication method for a terminal is also disclosed.

A base station includes: a controller that performs control to transmit a plurality of signals that is common to each terminal to a terminal located in a coverage area of its own base station by transmitting the plurality of signals at the same timing while frequency multiplexing the plurality of signals on a frequency domain in an area where the signals can be transmitted simultaneously using a beam within the coverage area, and transmitting the plurality of signals a plurality of times while changing the area; and an antenna that transmits the plurality of signals area by area while changing a direction of the beam under the control of the controller.

A signal transmission circuit element, a multiplexer circuit element and a demultiplexer circuit element are disclosed. The signal transmission circuit element is connected among multiple electronic modules so as to transmit an electrical signal. The signal transmission circuit element includes an input terminal, an input equalizer, an output driver and an output terminal. The input terminal is for inputting an electrical signal to the input equalizer. The output driver is electrically connected to the input equalizer. The output terminal is electrically connected to the output driver so as to output the electrical signal. Accordingly, after the input terminal receives the electrical signal, the input equalizer can perform gain compensation on the electrical signal, and then an output capacitance of the electrical signal is driven by the output driver and outputted through the output terminal.