A high-speed serial interface is provided. In one aspect, the high-speed serial interface uses three phase modulation for jointly encoding data and clock information. Accordingly, the need for de-skewing circuitry at the receiving end of the interface is eliminated, resulting in reduced link start-up time and improved link efficiency and power consumption. In one embodiment, the high-speed serial interface uses fewer signal conductors than conventional systems having separate conductors for data and clock information. In another embodiment, the serial interface allows for data to be transmitted at any speed without the receiving end having prior knowledge of the transmission data rate. In another aspect, the high-speed serial interface uses polarity encoded three phase modulation for jointly encoding data and clock information. This further increases the link capacity of the serial interface by allowing for more than one bit to be transmitted in any single baud interval.

A high-speed serial interface is provided. In one aspect, the high-speed serial interface uses three phase modulation for jointly encoding data and clock information. Accordingly, the need for de-skewing circuitry at the receiving end of the interface is eliminated, resulting in reduced link start-up time and improved link efficiency and power consumption. In one embodiment, the high-speed serial interface uses fewer signal conductors than conventional systems having separate conductors for data and clock information. In another embodiment, the serial interface allows for data to be transmitted at any speed without the receiving end having prior knowledge of the transmission data rate. In another aspect, the high-speed serial interface uses polarity encoded three phase modulation for jointly encoding data and clock information. This further increases the link capacity of the serial interface by allowing for more than one bit to be transmitted in any single baud interval.

System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Information is transmitted in N-phase polarity encoded symbols. Data is encoded in multi-bit symbols, and the multi-bit symbols are transmitted on a plurality of connectors. The multi-bit symbols may be transmitted by mapping the symbols to a sequence of states of the plurality of connectors, and driving the connectors in accordance with the sequence of states. The timing of the sequence of states is determinable at a receiver at each transition between sequential states. The state of each connector may be defined by polarity and direction of rotation of a multi-phase signal transmitted on the each connector.

System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Information is transmitted in N-phase polarity encoded symbols. Data is encoded in multi-bit symbols, and the multi-bit symbols are transmitted on a plurality of connectors. The multi-bit symbols may be transmitted by mapping the symbols to a sequence of states of the plurality of connectors, and driving the connectors in accordance with the sequence of states. The timing of the sequence of states is determinable at a receiver at each transition between sequential states. The state of each connector may be defined by polarity and direction of rotation of a multi-phase signal transmitted on the each connector.

A device, network, and method for communications with spatial-specific sensing is provided. In an embodiment, a method in a first communication node for providing contention-based transmission from the first communication node in a network to a second communication node includes determining, by the first communication node, a transmission direction, the transmission direction characterized by a digital beamforming direction and an analog beamsteering direction; performing, by the first communication node, spatial-specific carrier sensing in accordance with a sensing direction associated with the transmission direction; determining, by the first communication node, a channel status of a channel along the sensing direction according to the spatial-specific carrier sensing; and transmitting, by the first communication node, a transmission along the transmission direction.

A disclosed information processing apparatus includes a memory and a processor coupled to the memory. And the processor is configured to detect that a first apparatus is connected to a first network port, change network settings of the information processing apparatus into first network settings for the first network port, upon detecting that the first apparatus is connected to the first network port, and switch transmission paths in the information processing apparatus to enable the first apparatus to communicate using the first network port, upon detecting that the first apparatus is connected to the first network port.

A disclosed information processing apparatus includes a memory and a processor coupled to the memory. And the processor is configured to detect that a first apparatus is connected to a first network port, change network settings of the information processing apparatus into first network settings for the first network port, upon detecting that the first apparatus is connected to the first network port, and switch transmission paths in the information processing apparatus to enable the first apparatus to communicate using the first network port, upon detecting that the first apparatus is connected to the first network port.

An intelligent network patch field management system is provided that includes active electronic hardware, firmware, mechanical assemblies, cables, and software that guide, monitor, and report on the process of connecting and disconnecting patch cords plugs in an interconnect or cross-connect patching environment. The system is also capable of monitoring patch cord connections to detect insertions or removals of patch cords or plugs. In addition, the system can map embodiments of patch fields.

Techniques are provided for fallback authorization routing. A merchant processor may receive authorization requests from one or more merchant systems. These authorization requests may be to authorize a transaction. The merchant processor may transmit these authorization requests over a first communication channel to an acquirer processor, which may then forward the requests to a payment network. If the merchant processor determines that the acquirer processor is not receiving the authorization requests, or is otherwise unavailable, the merchant processor may, as a fallback, transmit the authorization requests directly to the payment network through a second communication channel, thereby bypassing the acquirer processor. When the merchant processor receives some indication that the acquirer processor is available to process authorization requests, new authorization requests can be transmitted to the acquirer processor via the first communication channel.

A system for transmitting control systems over twisted pair cabling. The system includes a first microcontroller transmitting a first single ended signal and receiving a second single ended signal. It also includes a first differential transmitter coupled to the first microcontroller for receiving the first single ended signal from the first microcontroller and converting it to a differential signal over a first differential line and a second differential line; and, a first differential receiver coupled to the first microcontroller for receiving a third differential line and a fourth differential line and converting it to a differential receiver signal, the differential receiver signal coupled to the second single ended signal. The system has a first transformer having first, second, third, and fourth center-tapped coils, the first differential line coupled to the center tap of the first coil, the second differential line coupled to the center tap of the fourth coil, the third differential line coupled to the center tap of the second coil, and the fourth differential line coupled to the center tap of the third coil, whereby the common mode of the first transformer is used to transmit a first control signal and to receive control signal responses over the twisted pair at the first processor.