A low-latency network device and method for treating serial data comprising an oscillator generating a device-wide clock; a receiving physical medium attachment (PMA) having an internal data width, a symbol timing synchronization module configured to receive the parallelized sample stream; and detect therefrom synchronized bit values corresponding to bit values of the received serial data; and a physical convergence sublayer (PCS). The PMA is configured to receive the serial data, deserialize the serial data based on the device-wide clock and internal data width, whereby the received serial data is oversampled, the oversampling of the received serial data being asynchronous relative to a timing of the received serial data, and output a parallelized sample stream. The PCS is configured to receive the synchronized bit values; and delineate packets therefrom to provide packet-delineated parallelized data. The PMA, the symbol timing synchronization module and the PCS are all driven by the device-wide clock.

A low-latency network device and method for treating serial data comprising an oscillator generating a device-wide clock; a receiving physical medium attachment (PMA) having an internal data width, a symbol timing synchronization module configured to receive the parallelized sample stream; and detect therefrom synchronized bit values corresponding to bit values of the received serial data; and a physical convergence sublayer (PCS). The PMA is configured to receive the serial data, deserialize the serial data based on the device-wide clock and internal data width, whereby the received serial data is oversampled, the oversampling of the received serial data being asynchronous relative to a timing of the received serial data, and output a parallelized sample stream. The PCS is configured to receive the synchronized bit values; and delineate packets therefrom to provide packet-delineated parallelized data. The PMA, the symbol timing synchronization module and the PCS are all driven by the device-wide clock.

A UE may determine a frame structure for narrowband communications, the frame structure corresponding to one frame structure from a group of TDD frame structures of different downlink and uplink subframe configurations. The UE receives configuration information indicating a first carrier to monitor for a BCH and/or a SIB1. Then, the UE receives a PSS, an SSS, and the BCH and/or the SIB1 using the frame structure determined for the narrowband communications. The first carrier that is used to receive the BCH and/or the SIB1 may be different from a second carrier used to receive one or more of the PSS or the SSS.

A UE may determine a frame structure for narrowband communications, the frame structure corresponding to one frame structure from a group of TDD frame structures of different downlink and uplink subframe configurations. The UE receives configuration information indicating a first carrier to monitor for a BCH and/or a SIB1. Then, the UE receives a PSS, an SSS, and the BCH and/or the SIB1 using the frame structure determined for the narrowband communications. The first carrier that is used to receive the BCH and/or the SIB1 may be different from a second carrier used to receive one or more of the PSS or the SSS.

There is a need to support narrowband TDD frame structure for narrowband communications. The present disclosure provides a solution by supporting one or more narrowband TDD frame structure(s) for narrowband communications. In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may determine a narrowband communication frame structure comprising a FDD mode or a TDD mode and a particular TDD frame structure for narrowband communications from a group of narrowband TDD frame structures. The apparatus may determine a periodicity, subframe number, and transmission sequence associated with a SSS based at least in part on the narrowband TDD frame structure. The apparatus may transmit the SSS using the narrowband TDD frame structure determined for the narrowband communications. In one aspect, the SSS may be transmitted in a same subframe within a frame and at a periodicity of 2 or more frames.

There is a need to support narrowband TDD frame structure for narrowband communications. The present disclosure provides a solution by supporting one or more narrowband TDD frame structure(s) for narrowband communications. In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may determine a narrowband communication frame structure comprising a FDD mode or a TDD mode and a particular TDD frame structure for narrowband communications from a group of narrowband TDD frame structures. The apparatus may determine a periodicity, subframe number, and transmission sequence associated with a SSS based at least in part on the narrowband TDD frame structure. The apparatus may transmit the SSS using the narrowband TDD frame structure determined for the narrowband communications. In one aspect, the SSS may be transmitted in a same subframe within a frame and at a periodicity of 2 or more frames.

A low-latency network device and method for treating serial data comprising an oscillator generating a device-wide clock; a receiving physical medium attachment (PMA) having an internal data width, a symbol timing synchronization module configured to receive the parallelized sample stream; and detect therefrom synchronized bit values corresponding to bit values of the received serial data; and a physical convergence sublayer (PCS). The PMA is configured to receive the serial data, deserialize the serial data based on the device-wide clock and internal data width, whereby the received serial data is oversampled, the oversampling of the received serial data being asynchronous relative to a timing of the received serial data, and output a parallelized sample stream. The PCS is configured to receive the synchronized bit values; and delineate packets therefrom to provide packet-delineated parallelized data. The PMA, the symbol timing synchronization module and the PCS are all driven by the device-wide clock.

A low-latency network device and method for treating serial data comprising an oscillator generating a device-wide clock; a receiving physical medium attachment (PMA) having an internal data width, a symbol timing synchronization module configured to receive the parallelized sample stream; and detect therefrom synchronized bit values corresponding to bit values of the received serial data; and a physical convergence sublayer (PCS). The PMA is configured to receive the serial data, deserialize the serial data based on the device-wide clock and internal data width, whereby the received serial data is oversampled, the oversampling of the received serial data being asynchronous relative to a timing of the received serial data, and output a parallelized sample stream. The PCS is configured to receive the synchronized bit values; and delineate packets therefrom to provide packet-delineated parallelized data. The PMA, the symbol timing synchronization module and the PCS are all driven by the device-wide clock.

Disclosed embodiments provide an interface circuit for the transfer of data from a synchronous circuit to an asynchronous circuit. Data from the synchronous circuit is received into a memory in the interface circuit. The data in the memory is then sent to the asynchronous circuit based on an instruction in a circular buffer that is part of the interface circuit. Processing elements within the interface circuit execute instructions contained within the circular buffer. The circular buffer rotates to provide new instructions to the processing elements. Flow control paces the data from the synchronous circuit to the asynchronous circuit.

Disclosed embodiments provide an interface circuit for the transfer of data from a synchronous circuit to an asynchronous circuit. Data from the synchronous circuit is received into a memory in the interface circuit. The data in the memory is then sent to the asynchronous circuit based on an instruction in a circular buffer that is part of the interface circuit. Processing elements within the interface circuit execute instructions contained within the circular buffer. The circular buffer rotates to provide new instructions to the processing elements. Flow control paces the data from the synchronous circuit to the asynchronous circuit.