Method and system for providing data monitoring and management including RF communication link over which a transmitter and a receiver is configured to communicate, the transmitter configured to periodically transmit a data packet associated with a detected analyte level received from an analyte sensor, and the receiver configured to identify the transmitter as the correct transmitter for which it is configured to receive the data packets, and to continue to receive the data packets from the transmitter once the transmitter identification has been verified, is provided.

An information processing apparatus is provided which includes a transmission unit for transmitting a query request for querying another device for a count value held by such other device, a reception unit for receiving a return of the count value from such other device, a correction unit for performing, at a predetermined period, correction processing for synchronizing sampling frequency with such other device based on the received count value, and a reproduction unit for reproducing content in synchronization with such other device based on the sampling frequency. The correction unit corrects by taking into account a Round Trip Time between the transmission of the query request and the reception of the return and residual difference occurred at a previous correction time.

A phase interpolator includes a current generating circuit, a current controlling circuit and a signal generating circuit, wherein the current generating circuit is arranged to generate a current; and the current controlling circuit is arranged to generate a control signal to the current generating circuit to control a current value of the current. The signal generating circuit includes a capacitor, wherein the signal generating circuit generates a phase interpolation signal by using the capacitor to receive the current, wherein a phase of the phase interpolation signal is varied according to the current.

Methods, apparatus, and systems for data communication over a multi-wire, multi-phase interface are disclosed. A method of calibration includes configuring a 3-phase signal to include a high frequency component and a low frequency component during a calibration period, and transmitting a version of the 3-phase signal on each wire of a 3-wire interface. The version of the 3-phase signal transmitted on each wire is out-of-phase with the versions of the 3-phase signal transmitted on each of the other wires of the 3-wire interface. The 3-phase signal may be configured to enable a receiver to determine certain operating parameters of the 3-wire interface.

The present disclosure discloses a two-point sampling optimized method and system for sinusoidal excitation-based frequency response measurement. A plurality of points are sampled at equal intervals within the starting frequency and ending frequency range as initial information, the interpolation error of each sub-frequency band is estimated according to existing sampling information, the sub-frequency band with the largest interpolation error is selected, two new sampling points are added within the sub-frequency band, and the above steps are repeated until the quantity of sampling points reaches the total quantity set by a user; and the user is asked whether new sampling points need to be added, if so, after the user specifies a new quantity of sampling points, the interpolation error of each sub-frequency band is estimated again and sampling continues, otherwise, the sampling ends. The present improves the practicality of a sinusoidal excitation-based frequency response measurement method.

Various embodiments of the present invention solve the problem of generating intermediate-time information useable to drive ZFE adaptation (for example, in connection with a digital receiver). Further, various embodiments of the present invention increase flexibility by enabling user-specified over-peaking and/or under-peaking (i.e. configurable equalizer tuning) with respect to a ZFE convergence (or lock) criterion.

Described herein are technologies related to an implementation of a digital-to-time converter (DTC) circuitry that utilizes a first interpolation and a second and finer interpolation to increase interpolation ranges. The DTC circuitry generates a fine-phase modulated signal generating at least two correlated signals, and generating coarse and fine interpolations of the correlated signals.

The present invention relates generally to integrated circuits. More particularly, the present invention provides a circuit and method for regulating a voltage for a high speed serializer/deserializer (SerDes) device. But it will be recognized that the technique can be used for regulating memory devices (e.g., DDR 4 SDRAM devices, DDR4 register devices, DDR4 controller devices), and other high speed data applications. In various embodiments, phase-interpolator is implemented in conjunction with a delay-lock loop (DLL) and an SR latch, where one or more outputs of the DLL is used by the SR latch. Additionally, such techniques can be used for a variety of applications such as network and/or computer storage systems, computer servers, hand held computing devices, portable computing devices, computer systems, network appliances and/or switches, routers, and gateways, and the like.

The present invention relates generally to integrated circuits. More particularly, the present invention provides a circuit and method for regulating a voltage for a high speed serializer/deserializer (SerDes) device. But it will be recognized that the technique can be used for regulating memory devices (e.g., DDR 4 SDRAM devices, DDR4 register devices, DDR4 controller devices), and other high speed data applications. In various embodiments, phase-interpolator is implemented in conjunction with a delay-lock loop (DLL) and an SR latch, where one or more outputs of the DLL is used by the SR latch. Additionally, such techniques can be used for a variety of applications such as network and/or computer storage systems, computer servers, hand held computing devices, portable computing devices, computer systems, network appliances and/or switches, routers, and gateways, and the like.

Techniques for pilot-aided carrier frequency and phase synchronization may use a three-pass process. In a first pass, initial frequency offset may be addressed, and a frame start time may be established. In a second pass, a fine frequency correction may be performed. In a third pass, phase variation may be tracked and corrected using a minimum set of pilot symbols.