H04L9/16

Public Key Storage with Secure Remote Update Capability
20230049387 · 2023-02-16 ·

The disclosed embodiments relate to a memory device. In one embodiment, a memory device is disclosed comprising a storage array, the storage array including a first region, the first region storing a server public key associated with a server, and a key table; and a controller configured to: receive a message from the server, the message including a command modifying the key table, validate the message using the server public key, and modify the key table based on the message.

Public Key Storage with Secure Remote Update Capability
20230049387 · 2023-02-16 ·

The disclosed embodiments relate to a memory device. In one embodiment, a memory device is disclosed comprising a storage array, the storage array including a first region, the first region storing a server public key associated with a server, and a key table; and a controller configured to: receive a message from the server, the message including a command modifying the key table, validate the message using the server public key, and modify the key table based on the message.

SECURE INVERSE SQUARE ROOT COMPUTATION SYSTEM, SECURE NORMALIZATION SYSTEM, METHODS THEREFOR, SECURE COMPUTATION APPARATUS, AND PROGRAM

The bit decomposition unit (11) generates a bit representation lap {a.sub.0}, . . . , {a.sub.λ−1} of a. A first bit sequence generator (12) calculates {a′.sub.i}={a.sub.i}∨{a.sub.i+1} to generate {a′.sub.0}, . . . , {a′.sub.λ′−1}. A flag sequence generator (13) generates {x.sub.0}, . . . , {x.sub.λ′−1} indicating a most significant bit of {a′.sub.0}, . . . , {a′.sub.λ′−1}. A normalization multiplier generator (14) generates [c′] by bit-connecting {x.sub.λ′−1}, . . . , {x.sub.0}. A second bit sequence generator (15) sets {a″.sub.i}={a.sub.2i} to generate {a″.sub.0}, . . . . A flag calculator (16) sums {x.sub.j}{a′.sub.j} to calculate a share value {r}. A normalization unit (18) calculates [b]: =[c′][c′][2a] when r=1 and [b]: =[c′][c′][a] when r=0. A inverse square root calculator (19) calculates [w]: =[1/√b]*√2 when r=1, and [w]: =[1/√b] when r=0. An inverse normalization unit (20) multiplies [1/√a]: =[w][c′].

SECURE SQUARE ROOT COMPUTATION SYSTEM, SECURE NORMALIZATION SYSTEM, METHODS THEREFOR, SECURE COMPUTATION APPARATUS, AND PROGRAM

A flag sequence generator (12) generates {x.sub.0}, . . . , {x.sub.λ−11} indicating a msb of a. A bit sequence generator (13) calculates {y.sub.i}:={x.sub.2i} XOR {x.sub.2i+1} to generate {y.sub.0}, . . . , {y.sub.λ′−1}. A flag calculator (14) calculates an exclusive logical sum of all {x.sub.j} to calculate [r] for each odd j. A public value multiplier setting-unit (16) sets r′ that becomes √2 when λ is an odd and 1 when λ is an even. A normalization multiplier generator (17) bit-connects {y.sub.0}, . . . to generate [c′]. A normalization multiplier generator (18) bit-connects {x.sub.λ−1}, . . . to generate [c]. A normalizer (19) calculates [b]:=[a][c]. A square root calculator (20) calculates [w]:=[√b]*(r′/√2) when r=1, and [w′]:=[√b]*r′ when r=0. An inverse normalizer (21) calculates [w][c′] and performs λ′ bits right-shift.

SECURE BOOT WITH RESISTANCE TO DIFFERENTIAL POWER ANALYSIS AND OTHER EXTERNAL MONITORING ATTACKS
20180004957 · 2018-01-04 ·

A method for device authentication comprises receiving, by processing hardware of a first device, a message from a second device to authenticate the first device. The processing hardware retrieves a secret value from secure storage hardware operatively coupled to the processing hardware. The processing hardware derives a validator from the secret value using a path through a key tree, wherein the path is based on the message, wherein deriving the validator using the path through the key tree comprises computing a plurality of successive intermediate keys starting with a value based on the secret value and leading to the validator, wherein each successive intermediate key is derived based on at least a portion of the message and a prior key. The first device then sends the validator to the second device.

SECURE BOOT WITH RESISTANCE TO DIFFERENTIAL POWER ANALYSIS AND OTHER EXTERNAL MONITORING ATTACKS
20180004957 · 2018-01-04 ·

A method for device authentication comprises receiving, by processing hardware of a first device, a message from a second device to authenticate the first device. The processing hardware retrieves a secret value from secure storage hardware operatively coupled to the processing hardware. The processing hardware derives a validator from the secret value using a path through a key tree, wherein the path is based on the message, wherein deriving the validator using the path through the key tree comprises computing a plurality of successive intermediate keys starting with a value based on the secret value and leading to the validator, wherein each successive intermediate key is derived based on at least a portion of the message and a prior key. The first device then sends the validator to the second device.

DATA ENCRYPTION AND DECRYPTION METHOD AND ENCRYPTION AND DECRYPTION DEVICE

An encryption method for data includes acquiring data to be encrypted and user information set relevant to the encryption, sending a key acquisition instruction to a terminal corresponding to the user information, receiving a key returned from the terminal corresponding to the user information, encrypting the data to be encrypted by using the key, and transmitting encrypted data to the terminal corresponding to the user information.

DATA ENCRYPTION AND DECRYPTION METHOD AND ENCRYPTION AND DECRYPTION DEVICE

An encryption method for data includes acquiring data to be encrypted and user information set relevant to the encryption, sending a key acquisition instruction to a terminal corresponding to the user information, receiving a key returned from the terminal corresponding to the user information, encrypting the data to be encrypted by using the key, and transmitting encrypted data to the terminal corresponding to the user information.

STOCHASTIC PROCESSING
20180011692 · 2018-01-11 · ·

A system, method, and device for stochastically processing data. There is an architect module operating on a processor configured to manage and control stochastic processing of data, a non-deterministic data pool module configured to provide a stream of non-deterministic values that are not derived from a function, a plurality of functionally equivalent data processing modules each configured to stochastically process data as called upon by the architect module, a data feed configured to feed a data set desired to be stochastically processed, and a structure memory module including a memory storage device and configured to provide sufficient information for the architect module to duplicate a predefined processing architecture and to record a utilized processing architecture.

STOCHASTIC PROCESSING
20180011692 · 2018-01-11 · ·

A system, method, and device for stochastically processing data. There is an architect module operating on a processor configured to manage and control stochastic processing of data, a non-deterministic data pool module configured to provide a stream of non-deterministic values that are not derived from a function, a plurality of functionally equivalent data processing modules each configured to stochastically process data as called upon by the architect module, a data feed configured to feed a data set desired to be stochastically processed, and a structure memory module including a memory storage device and configured to provide sufficient information for the architect module to duplicate a predefined processing architecture and to record a utilized processing architecture.