A memory module includes a first memory device, a second memory device, and a processing buffer circuit that is connected to the first memory device and the second memory device (independently of each other) and a host. A processing buffer circuit is provided, which includes a processing circuit and a buffer. The processing circuit processes at least one of data received from the host, data stored in the first memory device, or data stored in the second memory device based on a processing command received from the host. The buffer is configured to store data processed by the processing circuit. The processing buffer circuit is configured to communicate with the host in compliance with a DDR SDRAM standard.

A method for displaying an animation by a display chip of an electronic device, which includes a non-volatile memory and a random-access memory. The display chip includes a video output register and a display register. The method includes a first static programming phase including configuring the video output register; writing n images in the memory, n being an integer higher than or equal to two; writing into the memory of a plurality of nodes, such that each node includes the address in the memory of at least one portion of an image, as well as the address of the following node in the memory, the last node including the address in the random-access memory of the first node; and configuring the display register. The method also includes a second phase in which the n images are read by the display chip by the display register, to display the animation.

Disclosed are a signal processing device and an image display apparatus including the same. The signal processing device and the image display apparatus including the same according to an embodiment of the present disclosure includes: a first decoder to reconstruct image data received from an external electronic device, an encoder to compress the image data reconstructed in the first decoder, a memory to store the image data compressed in the encoder, and a second decoder to reconstruct the image data stored in the memory. Accordingly, despite of the increases of the amount of the input image data and the bandwidth thereof, the image data may be stored in the memory efficiently.

Systems, methods, and devices implement video streaming. Methods include receiving video data from a video source, the video data comprising at least one video frame, and determining a plurality of store parameters associated with a store operation and a plurality of fetch parameters associated with a fetch operation for a portion of the video data, wherein the plurality of store parameters and the plurality of fetch parameters identify whether a fetch unit or a store unit should be stalled. Methods also include implementing a store operation in a buffer for a designated number of lines of the video data based on the plurality of store parameters. Methods additionally include implementing a fetch operation from the buffer for the designated number of lines of the video data based on the plurality of fetch parameters.

This disclosure describes efficient communication of surface texture data between system on a chip (SOC) integrated circuits. An example system includes a first integrated circuit and a second integrated circuit communicatively coupled to the first integrated circuit by a video communication interface. The first integrated generates a superframe in a video frame of the video communication interface for transmission to the second integrated circuit. The superframe includes multiple subframe payloads that carry surface texture data to be updated in the frame and corresponding subframe headers that include parameters of the subframe payloads. The second integrated circuit includes a direct access memory (DMA) controller. The DMA upon receipt of the superframe, writes the surface texture data within each of the subframe payloads directly to an allocated location in memory based on the parameters included in the corresponding one of the subframe headers.

An example display device includes a display; a memory configured to store a plurality of applications that provide a content playback service; and a processor configured to: store information on the plurality of applications, information on a plurality of contents, and information on a point of time when playback is stopped in the memory when the playback of the plurality of contents played through the plurality of applications is stopped, and display a user interface (UI) screen for playing the plurality of contents from the point of time when the playback is stopped on the display using the information stored in the memory, when an application that provides a continuous content playback service is executed.

A storage system and method for time-based data retrieval are provided. In one embodiment, a controller of the storage system is configured to receive time information from a host; receive a write command from the host, wherein the write command comprises a logical block address; and create a time-to-logical-block-address map from the time information and the logical block address received from the host. Other embodiments are provided.

Technologies for coordinating access to packets include a network device. The network device is to establish a ring in a memory of the network device. The ring includes a plurality of slots. The network device is also to allocate cores to each of an input stage, an output stage, and a worker stage. The worker stage is to process data in a data packet with an associated worker function. The network device is also to add, with the input stage, an entry to a slot in the ring representative of a data packet received with a network interface controller of the network device, access, with the worker stage, the entry in the ring to process at least a portion of the data packet, and provide, with the output stage, the processed data packet to the network interface controller for transmission.

An image processing apparatus, comprising a memory that stores first image data, and a processor that includes an image associated information processing section, wherein the image associated information processing section, for the image data of a single frame that has been taken at a plurality of shooting conditions, within the first image data that has been stored in the memory, acquires image region information, relating to an image region in which shooting is carried out at different shooting conditions, and image associated information of the image region, associates the image region information and the image associated information and subjects the first image data to image processing, and generates second image data.

Provided is a data processing system. The system includes a data source, a data receiver, a plurality of source code data frame buffer regions, a data processing module and a state register. The data source is configured to generate a data frame, the data receiver is configured to receive the data frame, and write the data frame into one of a plurality of data frame buffer regions, each of the plurality of source code data frame buffer regions is configured to store a data frame to be processed, the data processing module is configured to perform subsequent processing on data and the state register is configured to store a state of the system and states of the plurality of source code data frame buffer regions.