An image processing device includes a modulation clock generator, a line synchronization signal generator, a line image sensor, and an image processor. The modulation clock generator is configured to generate the modulation clock by modulating a frequency of a reference clock at a predetermined modulation cycle. The line synchronization signal generator is configured to generate, on the basis of the modulation clock, a line synchronization signal whose line cycle varies from line to line. The line image sensor is configured to sequentially read an image of one line of a document at a timing corresponding to the line synchronization signal and to output image data. The image processor is configured to process the image data on the basis of the modulation clock.

A data processing device includes a data processing circuit and a data processing control circuit. The data processing circuit is configured to perform data processing on processing target data by use of an external clock, the processing target data being included in a data signal received from an outside, the external clock being included in the data signal. The data processing control circuit is configured to detect a state of the external clock and control execution of the data processing on the processing target data in accordance with the state of the external clock. The data processing control circuit is configured to operate with a clock having a lower impedance than an impedance of the external clock, and discard the processing target data received during a period in which an abnormality of the external clock is detected, in a case of detecting the abnormality of the external clock.

A system includes a mirror controller driving fast and slow axis mirrors of a projector with fast and slow axis drive signals to reflect a collimated light beam in a scan pattern across the target. The scan pattern includes trace lines which cause display of an input video stream on the target, and retrace lines which operate to return the slow axis mirror to a proper location to begin a next frame of the scan pattern. The slow axis drive signal is generated to maintain a number of trace lines in each frame of the scan pattern constant across frames, but the slow axis drive signal is modified to lock a phase and frequency of the displayed video to a phase and frequency of the input video stream by changing a number of retrace lines in each frame of the scan pattern on a frame-by-frame basis by a non-integer number.

A data processing device includes a data processing circuit and a data processing control circuit. The data processing circuit is configured to perform data processing on processing target data by use of an external clock, the processing target data being included in a data signal received from an outside, the external clock being included in the data signal. The data processing control circuit is configured to detect a state of the external clock and control execution of the data processing on the processing target data in accordance with the state of the external clock. The data processing control circuit is configured to operate with a clock having a lower impedance than an impedance of the external clock, and discard the processing target data received during a period in which an abnormality of the external clock is detected, in a case of detecting the abnormality of the external clock.

An image forming apparatus which is capable of reducing a load on a data bus therein when controlling an image reading apparatus depending on its image processing capability. When acquired identification information about the image forming apparatus is included in a clock control table 600, a clock frequency for controlling hardware of the image reading apparatus in accordance with the clock control table 600, while setting the clock frequency therefor to a default setting of the clock control table 600 when the acquired identification information is not included in the clock control table 600, wherein a minimum value of clock frequencies in the clock control table 600 is set as the default setting of the clock control table 600.

An image forming apparatus which is capable of reducing a load on a data bus therein when controlling an image reading apparatus depending on its image processing capability. When acquired identification information about the image forming apparatus is included in a clock control table 600, a clock frequency for controlling hardware of the image reading apparatus in accordance with the clock control table 600, while setting the clock frequency therefor to a default setting of the clock control table 600 when the acquired identification information is not included in the clock control table 600, wherein a minimum value of clock frequencies in the clock control table 600 is set as the default setting of the clock control table 600.

An image forming apparatus which is capable of reducing a load on a data bus therein when controlling an image reading apparatus depending on its image processing capability. When acquired identification information about the image forming apparatus is included in a clock control table 600, a clock frequency for controlling hardware of the image reading apparatus in accordance with the clock control table 600, while setting the clock frequency therefor to a default setting of the clock control table 600 when the acquired identification information is not included in the clock control table 600, wherein a minimum value of clock frequencies in the clock control table 600 is set as the default setting of the clock control table 600.

An image processing device includes a modulation clock generator, a line synchronization signal generator, a line image sensor, and an image processor. The modulation clock generator is configured to generate the modulation clock by modulating a frequency of a reference clock at a predetermined modulation cycle. The line synchronization signal generator is configured to generate, on the basis of the modulation clock, a line synchronization signal whose line cycle varies from line to line. The line image sensor is configured to sequentially read an image of one line of a document at a timing corresponding to the line synchronization signal and to output image data. The image processor is configured to process the image data on the basis of the modulation clock.

An image forming apparatus which is capable of reducing a load on a data bus therein when controlling an image reading apparatus depending on its image processing capability. When acquired identification information about the image forming apparatus is included in a clock control table 600, a clock frequency for controlling hardware of the image reading apparatus in accordance with the clock control table 600, while setting the clock frequency therefor to a default setting of the clock control table 600 when the acquired identification information is not included in the clock control table 600, wherein a minimum value of clock frequencies in the clock control table 600 is set as the default setting of the clock control table 600.