An image processing device includes a modulation clock generator, a line synchronization signal generator, a line image sensor, and an image processor. The modulation clock generator is configured to generate the modulation clock by modulating a frequency of a reference clock at a predetermined modulation cycle. The line synchronization signal generator is configured to generate, on the basis of the modulation clock, a line synchronization signal whose line cycle varies from line to line. The line image sensor is configured to sequentially read an image of one line of a document at a timing corresponding to the line synchronization signal and to output image data. The image processor is configured to process the image data on the basis of the modulation clock.

A data processing device includes a data processing circuit and a data processing control circuit. The data processing circuit is configured to perform data processing on processing target data by use of an external clock, the processing target data being included in a data signal received from an outside, the external clock being included in the data signal. The data processing control circuit is configured to detect a state of the external clock and control execution of the data processing on the processing target data in accordance with the state of the external clock. The data processing control circuit is configured to operate with a clock having a lower impedance than an impedance of the external clock, and discard the processing target data received during a period in which an abnormality of the external clock is detected, in a case of detecting the abnormality of the external clock.

A data processing device includes a data processing circuit and a data processing control circuit. The data processing circuit is configured to perform data processing on processing target data by use of an external clock, the processing target data being included in a data signal received from an outside, the external clock being included in the data signal. The data processing control circuit is configured to detect a state of the external clock and control execution of the data processing on the processing target data in accordance with the state of the external clock. The data processing control circuit is configured to operate with a clock having a lower impedance than an impedance of the external clock, and discard the processing target data received during a period in which an abnormality of the external clock is detected, in a case of detecting the abnormality of the external clock.

An aspect of the disclosure relates to a semiconductor device including a semiconductor element, a connection terminal configured to output a signal based on an output of the semiconductor element, a protection circuit connected to the connection terminal, and a voltage limiting element connected to the connection terminal, wherein the protection circuit is connected to a first power supply line having a first potential and a second power supply line having a second potential lower than the first potential, and wherein a potential supplied to the voltage limiting element is higher than the second potential and lower than the first potential.

An image processing device includes a modulation clock generator, a line synchronization signal generator, a line image sensor, and an image processor. The modulation clock generator is configured to generate the modulation clock by modulating a frequency of a reference clock at a predetermined modulation cycle. The line synchronization signal generator is configured to generate, on the basis of the modulation clock, a line synchronization signal whose line cycle varies from line to line. The line image sensor is configured to sequentially read an image of one line of a document at a timing corresponding to the line synchronization signal and to output image data. The image processor is configured to process the image data on the basis of the modulation clock.

An aspect of the disclosure relates to a semiconductor device including a semiconductor element, a connection terminal configured to output a signal based on an output of the semiconductor element, a protection circuit connected to the connection terminal, and a voltage limiting element connected to the connection terminal, wherein the protection circuit is connected to a first power supply line having a first potential and a second power supply line having a second potential lower than the first potential, and wherein a potential supplied to the voltage limiting element is higher than the second potential and lower than the first potential.