Patent classifications
H04N25/44
Solid-state imaging apparatus and imaging apparatus
Time deviation between event detection and gradation acquisition is reduced. A solid-state imaging apparatus according to an embodiment includes: a pixel array unit (300) including a plurality of pixel blocks (310) arrayed in a matrix; and a drive circuit (211) that generates a pixel signal in a first pixel block in which firing of an address event has been detected among the plurality of pixel blocks, each of the plurality of pixel blocks including a first photoelectric conversion element (331) that generates an electric charge according to an amount of incident light, a detection unit (400) that detects the firing of the address event based on the electric charge generated in the first photoelectric conversion element, a second photoelectric conversion element (321) that generates an electric charge according to an amount of incident light, and a pixel circuit (322, 323, 324, 325, 326) that generates a pixel signal based on the electric charge generated in the second photoelectric conversion element.
Solid-state imaging apparatus and imaging apparatus
Time deviation between event detection and gradation acquisition is reduced. A solid-state imaging apparatus according to an embodiment includes: a pixel array unit (300) including a plurality of pixel blocks (310) arrayed in a matrix; and a drive circuit (211) that generates a pixel signal in a first pixel block in which firing of an address event has been detected among the plurality of pixel blocks, each of the plurality of pixel blocks including a first photoelectric conversion element (331) that generates an electric charge according to an amount of incident light, a detection unit (400) that detects the firing of the address event based on the electric charge generated in the first photoelectric conversion element, a second photoelectric conversion element (321) that generates an electric charge according to an amount of incident light, and a pixel circuit (322, 323, 324, 325, 326) that generates a pixel signal based on the electric charge generated in the second photoelectric conversion element.
TECHNIQUES FOR PHASE DETECTION AUTOFOCUS
Methods, systems, and devices for techniques for phase detection autofocus (PDAF) are described. A device may receive a set of PDAF pixels and may rearrange the set of PDAF pixels into a first subset of pixels in a first line buffer and a second subset of pixels in a second line buffer. As part of a first output operation, the device may perform a uniformity correction on the first subset of pixels, output the first subset of pixels to a left, center, right (LCR) processing path, and write-back the corrected first subset of pixels to the first line buffer. As part of a second output operation, the device may perform a uniformity correction on the second subset of pixels, output the second subset of pixels to an LCR processing path and an interleaver, and pull the corrected first subset of pixels from the first line buffer to the interleaver.
Image sensor and imaging device including a plurality of semiconductor substrates
An image sensor includes: a first imaging region that captures an image of light entering through an optical system under a first imaging condition and generates a detection signal to perform focus detection of the optical system; and a second imaging region that captures an image of the light entering through the optical system under a second imaging condition other than the first imaging condition and generates an image signal.
Imaging apparatus, imaging system, imaging method, and imaging program including sequential recognition processing on units of readout
An imaging apparatus according to an embodiment includes: an imaging unit (10) having a pixel region in which a plurality of pixels is arranged; a readout controller (11) that controls readout of pixel signals from pixels included in the pixel region; a unit-of-readout controller (123) that controls a unit of readout that is set as a part of the pixel region and for which the readout controller performs the readout; and a recognition unit (14) that has learned training data for each of the units of readout. The recognition unit performs a recognition process on the pixel signal for each of the units of readout, and outputs a recognition result which is a result of the recognition process.
Image capture device with contemporaneous image correction mechanism
A hand-held or otherwise portable or spatial or temporal performance-based image capture device includes one or more lenses, an aperture and a main sensor for capturing an original main image. A secondary sensor and optical system are for capturing a reference image that has temporal and spatial overlap with the original image. The device performs an image processing method including capturing the main image with the main sensor and the reference image with the secondary sensor, and utilizing information from the reference image to enhance the main image. The main and secondary sensors are contained together within a housing.
Dynamic vision sensor architecture
A dynamic vision sensor (DVS) or change detection sensor reacts to changes in light intensity and in this way monitors how a scene changes. This disclosure covers both single pixel and array architectures. The DVS may contain one pixel or 2-dimensional or 1-dimensional array of pixels. The change of intensities registered by pixels are compared, and pixel addresses where the change is positive or negative are recorded and processed. Analyzing frames based on just three values for pixels, increase, decrease or unchanged, the proposed DVS can process visual information much faster than traditional computer vision systems, which correlate multi-bit color or gray level pixel values between successive frames.
EVENT-BASED COMPUTATIONAL PIXEL IMAGERS
A computational pixel imaging device that includes an array of pixel integrated circuits for event-based detection and imaging. Each pixel may include a digital counter that accumulates a digital number, which indicates whether a change is detected by the pixel. The counter may count in one direction for a portion of an exposure and count in an opposite direction for another portion of the exposure. The imaging device may be configured to collect and transmit key frames at a lower rate, and collect and transmit delta or event frames at a higher rate. The key frames may include a full image of a scene, captured by the pixel array. The delta frames may include sparse data, captured by pixels that have detected meaningful changes in received light intensity. High speed, low transmission bandwidth motion image video can be reconstructed using the key frames and the delta frames.
Imaging apparatus for downsizing an image sensor and a signal processor
The present invention relates to an imaging apparatus for realizing real time image display and the like while controlling the processing performance of an external circuit and the size of the circuit when outputting a large amount of data from an image sensor at a high speed, and is provided with (a) an image sensor including, a plurality of light receiving units disposed in rows and columns, an A/D conversion unit, a compression unit for compressing outputs from the A/D conversion unit row by row, and (b) a first data processing unit for thinning compressed data row by row, a first data decompression unit that decompresses outputs of the first data processing unit; and a first image processing unit which carries out a predetermined processing on outputs of the first data decompression unit.
FLAG-BASED READOUT ARCHITECTURE FOR EVENT-DRIVEN PIXEL MATRIX ARRAY
An event-driven sensor including: a pixel array; a column readout circuit coupled to column output lines of the pixel array, the column readout circuit comprising a plurality of groups of column register cells coupled in series with each other to propagate a first flag signal, wherein each column register cell is configured to activate a column event output signal when it receives the first flag signal while the detection of an event is indicated on the column output line; and a first bypassing circuit for each group of column register cells, the first bypassing circuits being coupled in series with each other to propagate the first flag signal.