In a solid-state imaging element that transfers data in a vertical direction, the number of times of transfer is reduced. The solid-state imaging element is provided with a plurality of storage units and a data transfer circuit. In the solid-state imaging element, each of the plurality of storage units is provided with a holding unit that holds predetermined reset data and signal data according to an amount of light, and an arithmetic circuit that obtains a difference between the reset data and the signal data to output as pixel data. Furthermore, the data transfer circuit in the solid-state imaging element transfers the output pixel data.

A camera array, an imaging device and/or a method for capturing image that employ a plurality of imagers fabricated on a substrate is provided. Each imager includes a plurality of pixels. The plurality of imagers include a first imager having a first imaging characteristics and a second imager having a second imaging characteristics. The images generated by the plurality of imagers are processed to obtain an enhanced image compared to images captured by the imagers. Each imager may be associated with an optical element fabricated using a wafer level optics (WLO) technology.

Provided is an image processing apparatus for correcting blinking defect noise contained in image data generated by an image sensor. The image sensor includes a pixels arranged two-dimensionally and reading circuits configured to read a pixel value. The image processing apparatus includes: an information acquisition unit configured to acquire noise information that is defined by associating positional information of the reading circuits or positional information of each of the pixels with feature data related to the blinking defect noise caused by the reading circuits; an estimation unit configured to estimate a random noise amount in a pixel of interest based on the feature data and a random noise model for estimating the random noise amount in the pixel of interest; and a correction unit configured to correct a pixel value of the pixel of interest based on the random noise amount estimated by the estimation unit.

An image sensor includes a pixel array including a first pixel and a second pixel which are connected to a first column line, and a row driver configured to control a read operation of the second pixel. A voltage of the first column line is determined based on a higher voltage among a voltage of a floating diffusion node of the first pixel and a voltage of a floating diffusion node of the second pixel during the read operation of the second pixel.

An image sensor includes a pixel array including a first pixel and a second pixel which are connected to a first column line, and a row driver configured to control a read operation of the second pixel. A voltage of the first column line is determined based on a higher voltage among a voltage of a floating diffusion node of the first pixel and a voltage of a floating diffusion node of the second pixel during the read operation of the second pixel.

A correlated double sampling (CDS) circuit, an operating method thereof, and an image sensor including the CDS circuit are disclosed. The CDS circuit includes a first comparator configured to operate based on a first bias current, and compare, with a ramp signal, a pixel voltage that is output from a pixel, during a first period and a fourth period during which the pixel operates in a low conversion gain (LCG) mode, a second comparator configured to operate based on a second bias current, and compare, with the ramp signal, the pixel voltage output from the pixel, during a second period and a third period during which the pixel operates in a high conversion gain (HCG) mode, the second period being after the first period, the third period being after the second period, and the fourth period being after the third period.

An image sensor includes a pixel configured to operate in a high conversion gain (HCG) mode and a low conversion gain (LCG) mode during a readout period, and a correlated double sampling (CDS) circuit configured to generate a comparison signal based on a ramp signal and a pixel voltage received from the pixel, wherein the CDS circuit includes a comparator configured to: receive the pixel voltage through a first input node, receive the ramp signal through a second input node based on an LCG reset signal or an LCG image signal being received as the pixel voltage, and receive the ramp signal through a third input node based on an HCG reset signal or an HCG image signal being received as the pixel voltage; and compare the ramp signal to the pixel voltage, and output the comparison signal corresponding to a comparison result.

An image sensor includes a pixel configured to operate in a high conversion gain (HCG) mode and a low conversion gain (LCG) mode during a readout period, and a correlated double sampling (CDS) circuit configured to generate a comparison signal based on a ramp signal and a pixel voltage received from the pixel, wherein the CDS circuit includes a comparator configured to: receive the pixel voltage through a first input node, receive the ramp signal through a second input node based on an LCG reset signal or an LCG image signal being received as the pixel voltage, and receive the ramp signal through a third input node based on an HCG reset signal or an HCG image signal being received as the pixel voltage; and compare the ramp signal to the pixel voltage, and output the comparison signal corresponding to a comparison result.

Provided is a multilayer imaging device capable of both securing a wide sensitive region and securing an accumulated amount of charges. An imaging device according to an embodiment comprises a pixel, the pixel including a photoelectric conversion layer (15); a first electrode (11) positioned close to a first surface of the photoelectric conversion layer and electrically connected to the photoelectric conversion layer; a second electrode (16) positioned on a second surface opposite to the first surface of the photoelectric conversion layer; a charge accumulation electrode (12) disposed close to the first surface of the photoelectric conversion layer and spaced apart from the first electrode in a direction parallel to the first surface; and a third electrode (200) disposed at a position to have a portion overlapping a gap between the first electrode and the charge accumulation electrode in a direction perpendicular to the first surface.

Solid-state imaging elements are disclosed. In one example, an upstream circuit block generates a predetermined reset level and a plurality of signal levels each corresponding to an exposure amount, and causes capacitive elements, different from each other, to hold them. A selection circuit sequentially performs control to connect the capacitive element in which the reset level is held to a predetermined downstream node, control to disconnect capacitive elements from the downstream node, and control to connect the capacitive element in which any of the plurality of signal levels is held to the downstream node. A downstream reset transistor initializes a level of the downstream node when the capacitive elements are disconnected from the downstream node. A downstream circuit sequentially reads the reset level and the plurality of signal levels via the downstream node